Maximum Clock Frequencies

Table 1. Maximum GCLK Generator Output Frequencies
Symbol Condition Max. Units
fGCLKGEN0 / fGCLK_MAIN Undivided 96 MHz
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3 Divided 66 MHz
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table 2. Maximum Peripheral Clock Frequencies
Symbol Description Max. Units
fCPU CPU clock frequency 48 MHz
fAHB AHB clock frequency 48 MHz
fAPBA APBA clock frequency 48 MHz
fAPBB APBB clock frequency 48 MHz
fAPBC APBC clock frequency 48 MHz
fGCLK_DPLL FDPLL96M Reference clock frequency 2 MHz
fGCLK_DPLL_32K FDPLL96M 32k Reference clock frequency 32 kHz
fGCLK_EIC EIC input clock frequency 48 MHz
fGCLK_FREQM_MSR FREQM Measure 48 MHz
fGCLK_FREQM_REF FREQM Reference 48 MHz
fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_4 EVSYS channel 4 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_5 EVSYS channel 5 input clock frequency 48 MHz
fGCLK_SERCOMx_SLOW Common SERCOM slow input clock frequency 5 MHz
fGCLK_SERCOM0_CORE SERCOM0 input clock frequency 48 MHz
fGCLK_SERCOM1_CORE SERCOM1 input clock frequency 48 MHz
fGCLK_SERCOM2_CORE SERCOM2 input clock frequency 48 MHz
fGCLK_SERCOM3_CORE SERCOM3 input clock frequency 48 MHz
fGCLK_TCC0, 1 TCCn input clock frequency 92 MHz
fGCLK_TCC2 TCC2 input clock frequency 48 MHz
fGCLK_TCn TCn input clock frequency 48 MHz
fGCLK_ADC0 ADC0 input clock frequency 48 MHz
fGCLK_PTC PTC input clock frequency 48 MHz
fGCLK_CCL CCL input clock frequency 48 MHz
fGCLK_AC AC digital input clock frequency 48 MHz