INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.

Name:: INTENSET
Offset:: 0x02
Reset:: 0x00
Access:: PAC Write-Protection

Bit7	6	5	4	3	2	1	0
							CKRDY
Access							R/W
Reset							0

Bit 0 – CKRDY: Clock Ready Interrupt Enable

Clock Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.

Value	Description
0	The Clock Ready interrupt is disabled.
1	The Clock Ready interrupt is enabled.