| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SAMPLING[31:24] | |||||||
| AccessW | W | W | W | W | W | W | W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SAMPLING[23:16] | |||||||
| AccessW | W | W | W | W | W | W | W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SAMPLING[15:8] | |||||||
| AccessW | W | W | W | W | W | W | W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SAMPLING[7:0] | |||||||
| AccessW | W | W | W | W | W | W | W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Input Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data Direction register (DIR).
The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled.
| Value | Description |
|---|---|
| 0 | The I/O pin input synchronizer is disabled. |
| 1 | The I/O pin input synchronizer is enabled. |