Interrupt Enable Set
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x04
Reset:
0x00000000
Access:
PAC Write-Protection
Bit3130292827262524
Access
Reset
Bit2322212019181716
Access
Reset
Bit15141312111098
Access
Reset
Bit76543210
CLKFAILOSC32KRDYXOSC32KRDY
AccessR/WR/WR/W
Reset000

Bit 2 – CLKFAIL: XOSC32K Clock Failure Detection Interrupt Enable

XOSC32K Clock Failure Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the XOSC32K Clock Failure interrupt.

ValueDescription
0 The XOSC32K Clock Failure Detection is disabled.
1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set.

Bit 1 – OSC32KRDY: OSC32K Ready Interrupt Enable

OSC32K Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt.

ValueDescription
0 The OSC32K Ready interrupt is disabled.
1 The OSC32K Ready interrupt is enabled.

Bit 0 – XOSC32KRDY: XOSC32K Ready Interrupt Enable

XOSC32K Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt.

ValueDescription
0 The XOSC32K Ready interrupt is disabled.
1 The XOSC32K Ready interrupt is enabled.