DPLL Prescaler
Name:
DPLLPRESC
Offset:
0x28
Reset:
0x00
Access:
PAC Write-Protection, Write-Synchronized
Bit76543210
PRESC[1:0]
AccessR/WR/W
Reset00

Bits 1:0 – PRESC[1:0]: Output Clock Prescaler

Output Clock Prescaler

These bits define the output clock prescaler setting.

ValueNameDescription
0x0 DIV1 DPLL output is divided by 1
0x1 DIV2 DPLL output is divided by 2
0x2 DIV4 DPLL output is divided by 4
0x3 Reserved