Status
Name:
STATUS
Offset:
0x0C
Reset:
0x00000000
Access:
-
Bit3130292827262524
Access
Reset
Bit2322212019181716
Access
Reset
Bit15141312111098
DPLLLDRTODPLLLTODPLLLCKFDPLLLCKR
AccessRRRR
Reset0000
Bit76543210
OSC48MRDYCLKSWCLKFAILXOSCRDY
AccessRRRR
Reset0000

Bit 11 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete

DPLL Loop Divider Ratio Update Complete

ValueDescription
0 DPLL Loop Divider Ratio Update Complete not detected.
1 DPLL Loop Divider Ratio Update Complete detected.

Bit 10 – DPLLLTO: DPLL Lock Timeout

DPLL Lock Timeout

ValueDescription
0 DPLL Lock time-out not detected.
1 DPLL Lock time-out detected.

Bit 9 – DPLLLCKF: DPLL Lock Fall

DPLL Lock Fall

ValueDescription
0 DPLL Lock fall edge not detected.
1 DPLL Lock fall edge detected.

Bit 8 – DPLLLCKR: DPLL Lock Rise

DPLL Lock Rise

ValueDescription
0 DPLL Lock rise edge not detected.
1 DPLL Lock fall edge detected.

Bit 4 – OSC48MRDY: OSC48M Ready

OSC48M Ready

ValueDescription
0 OSC48M is not ready.
1 OSC48M is stable and ready to be used as a clock source.

Bit 2 – CLKSW: XOSC Clock Switch

XOSC Clock Switch

ValueDescription
0 XOSC is not switched and provides the external clock or crystal oscillator clock.
1 XOSC is switched and provides the safe clock.

Bit 1 – CLKFAIL: XOSC Clock Failure

XOSC Clock Failure

ValueDescription
0 No XOSC failure detected.
1 A XOSC failure was detected.

Bit 0 – XOSCRDY: XOSC Ready

XOSC Ready

ValueDescription
0 XOSC is not ready.
1 XOSC is stable and ready to be used as a clock source.