| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CKSEL | ENABLE | SWRST | |||||
| Access | R/W | R/W | W | ||||
| Reset | 0 | 0 | 0 |
Clock Selection
The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32KHz is required for filtering) or by CLK_ULP32K (when power consumption is the priority).
This bit is not Write-Synchronized.
| Value | Description |
|---|---|
| 0 | The EIC is clocked by GCLK_EIC. |
| 1 | The EIC is clocked by CLK_ULP32K. |
Enable
Due to synchronization there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register will be set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not Enable-Protected.
| Value | Description |
|---|---|
| 0 | The EIC is disabled. |
| 1 | The EIC is enabled. |
Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.
This bit is not Enable-Protected.
| Value | Description |
|---|---|
| 0 | There is no ongoing reset operation. |
| 1 | The reset operation is ongoing. |