SYNCBUSY

Name:: SYNCBUSY
Offset:: 0x04
Reset:: 0x00000000
Access:: –

Bit31	30	29	28	27	26	25	24

Access
Reset
Bit23	22	21	20	19	18	17	16

Access
Reset
Bit15	14	13	12	11	10	9	8
					GENCTRL8	GENCTRL7	GENCTRL6
Access					R	R	R
Reset					0	0	0
Bit7	6	5	4	3	2	1	0
GENCTRL5	GENCTRL4	GENCTRL3	GENCTRL2	GENCTRL1	GENCTRL0		SWRST
AccessR	R	R	R	R	R		R
Reset0	0	0	0	0	0		0

Bit 0 – SWRST: SWRST Synchronization Busy

SWRST Synchronization Busy

This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete.

This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started.

Bits 2,3,4,5,6,7,8,9,10 – GENCTRLx: Generator Control x Synchronization Busy

Generator Control x Synchronization Busy

This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is complete, or when clock switching operation is complete.

This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is started.