Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name:
INTENSET
Offset:
0x0A
Reset:
0x0000
Access:
PAC Write-Protection
Bit15141312111098
OVFALARM0
AccessR/WR/W
Reset00
Bit76543210
PER7PER6PER5PER4PER3PER2PER1PER0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bit 15 – OVF: Overflow Interrupt Enable

Overflow Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.

Bit 8 – ALARM0: Alarm 0 Interrupt Enable

Alarm 0 Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm 0 Interrupt Enable bit, which enables the Alarm 0 interrupt.
ValueDescription
0 The Alarm 0 interrupt is disabled.
1 The Alarm 0 interrupt is enabled.

Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]

Periodic Interval n Interrupt Enable [n = 7..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt.
ValueDescription
0 Periodic Interval n interrupt is disabled.
1 Periodic Interval n interrupt is enabled.