Sleep Mode Controller

A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode.

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction.

Table 1. Sleep Mode Entry and Exit Table
Mode	Mode Entry	Wake-Up Sources
IDLE	SLEEPCFG.SLEEPMODE = IDLE	Synchronous ⁽²⁾ (APB, AHB), asynchronous ⁽¹⁾
STANDBY	SLEEPCFG.SLEEPMODE = STANDBY	Synchronous⁽³⁾, Asynchronous

Note:

Asynchronous: interrupt generated on generic clock, external clock, or external event.
Synchronous: interrupt generated on the APB clock.
Synchronous interrupt only for peripherals configured to run in standby.

Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.

The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below.

Table 2. Sleep Mode Overview
Mode	CPU clock	AHB clock	APB clock	Main clock	GCLK clocks	Oscillators		Regulator	RAM
Mode	CPU clock	AHB clock	APB clock	Main clock	GCLK clocks	ONDEMAND = 0	ONDEMAND = 1	Regulator	RAM
IDLE	Stop	Stop⁽²⁾	Stop⁽²⁾	Run	Run⁽¹⁾	Run	Run if requested	Main	Normal
STANDBY	Stop	Stop⁽²⁾	Stop⁽²⁾	Stop	Stop⁽²⁾	Run if requested or RUNSTDBY=1	Run if requested	LPVREG⁽³⁾	Low power⁽⁴⁾

Note:

Running if requested by peripheral.
Running during SleepWalking.
Regulator state is programmable by using STDBYCFG.VREGSMOD bits.
RAM state is programmable by using STDBYCFG.BBIASHS bit.