| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| IN[31:24] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IN[23:16] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IN[15:8] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IN[7:0] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
PORT Data Input Value
These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin.
These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin.