PORT Access Priority

The PORT is accessed by different systems:

• The ARM® CPU through the ARM® single-cycle I/O port (IOBUS)

• The ARM® CPU through the high-speed matrix and the AHB/APB bridge (APB)

• EVSYS through four asynchronous input events

The following priority is adopted:

1. ARM® CPU IOBUS (No wait tolerated)
2. APB
3. EVSYS input events

For input events that require different actions on the same I/O pin, refer to Events.