Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x00
Reset:
0x00000000
Access:
PAC Write-Protection
Bit3130292827262524
Access
Reset
Bit2322212019181716
Access
Reset
Bit15141312111098
Access
Reset
Bit76543210
BVDDSRDYBODVDDDETBODVDDRDY
AccessR/WR/WR/W
Reset000

Bit 2 – BVDDSRDY: BODVDD Synchronization Ready Interrupt Enable

BODVDD Synchronization Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the BODVDD Synchronization Ready Interrupt Enable bit, which disables the BODVDD Synchronization Ready interrupt.

ValueDescription
0 The BODVDD Synchronization Ready interrupt is disabled.
1 The BODVDD Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BODVDD Synchronization Ready Interrupt flag is set.

Bit 1 – BODVDDDET: BODVDD Detection Interrupt Enable

BODVDD Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the BODVDD Detection Interrupt Enable bit, which disables the BODVDD Detection interrupt.

ValueDescription
0 The BODVDD Detection interrupt is disabled.
1 The BODVDD Detection interrupt is enabled, and an interrupt request will be generated when the BODVDD Detection Interrupt flag is set.

Bit 0 – BODVDDRDY: BODVDD Ready Interrupt Enable

BODVDD Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the BODVDD Ready Interrupt Enable bit, which disables the BODVDD Ready interrupt.

ValueDescription
0 The BODVDD Ready interrupt is disabled.
1 The BODVDD Ready interrupt is enabled, and an interrupt request will be generated when the BODVDD Ready Interrupt flag is set.