Analog-to-Digital Converter (ADC) Characteristics

Table 1. Operating Conditions⁽¹⁾
Symbol	Parameters	Conditions	Min	Typ	Max	Unit
Res	Resolution		-	-	12	bits
Rs	Sampling rate		10	-	1000	ksps
fs	Sampling clock		10	-	1000	kHz
	Differential mode Number of ADC clock cycles SAMPCTRL.OFFCOMP=1	resolution 12 bit (CTRLC.RESSEL=0)	-	16	-	cycles
		resolution 10 bit (CTRLC.RESSEL=2)		14
		resolution 8 bit (CTRLC.RESSEL=3)		12
	Differential mode Number of ADC clock cycles SAMPCTRL.OFFCOMP=0 SAMPLEN corresponds to the decimal value of SAMPCTRL.SAMPLEN[5:0] register	resolution 12 bit (CTRLC.RESSEL=0)	-	SAMPLEN+13	-	cycles
		resolution 10 bit (CTRLC.RESSEL=2)		SAMPLEN+11
		resolution 8 bit (CTRLC.RESSEL=3)		SAMPLEN+9
	Single-ended mode Number of ADC clock cycles SAMPCTRL.OFFCOMP=1	resolution 12 bit (CTRLC.RESSEL=0)	-	16	-	cycles
		resolution 10 bit (CTRLC.RESSEL=2)		15
		resolution 8 bit (CTRLC.RESSEL=3)		13
	Single-ended mode Number of ADC clock cycles SAMPCTRL.OFFCOMP=0 SAMPLEN corresponds to the decimal value of SAMPCTRL.SAMPLEN[5:0] register	resolution 12 bit (CTRLC.RESSEL=0)	-	SAMPLEN+13	-	cycles
		resolution 10 bit (CTRLC.RESSEL=2)		SAMPLEN+12
		resolution 8 bit (CTRLC.RESSEL=3)		SAMPLEN+10
fadc	ADC Clock frequency	SAMPCTRL.OFFCOMP=1 or CTRLC.R2R=1	-	fs*16	-	Hz
fadc	ADC Clock frequency	SAMPCTRL.OFFCOMP=0	-	fs*13	-	Hz
Ts	Sampling time	SAMPCTRL.OFFCOMP=1 or CTRLC.R2R=1	250	-	25000	ns
	Sampling time	SAMPCTRL.OFFCOMP=0	76	-	7692
	Sampling time with DAC as input	SAMPCTRL.OFFCOMP=1 or CTRLC.R2R=1	3000	-	25000
	Sampling time with DAC as input	SAMPCTRL.OFFCOMP=0	3000	-	7692
	Conversion range	Differential mode	-VREF	-	+VREF	V
	Conversion range	Single-ended mode	0	-	VREF	V
Vref	Reference input	REFCTRL.REFCOMP=1	2	-	VDDANA-0.6	V
Vref	Reference input	REFCTRL.REFCOMP=0	VDDANA	-	VDDANA	V
Vin	Input channel range	-	0	-	VDDANA	V
Vcmin	Input common mode voltage	CTRLC.R2R=1	0.2	-	VREF-0.2	V
Vcmin	Input common mode voltage	CTRLC.R2R=0	VREF/2-0.2	-	VREF/2+0.2	V
CSAMPLE	Input sampling capacitance		-	1.6	4.5	pF
RSAMPLE	Input sampling on-resistance	For a sampling rate at 1 Msps	-	1000	-	Ω
Rref	Reference input source resistance		0	-	1000	kΩ

These values are based on simulation. These values are not covered by test limits in production or characterization.

Figure 1. ADC Analog Input AINx

The minimum sampling time t_samplehold for a given R_source can be found using this formula:

tsamplehold≥(Rsample+Rsource)×Csample×(n+2)×ln⁡(2)

For 12-bit accuracy:

tsamplehold≥(Rsample+Rsource)×Csample×9.7

where tsamplehold≥12×fADC .

Table 2. Differential Mode⁽¹⁾
Symbol	Parameter	Conditions		Measurement			Unit
				Min	Typ	Max
ENOB⁽²⁾	Effective Number of bits	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	10.0	10.7	11	bits
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	10.3	10.5	10.9
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	10.5	10.8	11.1
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	9.9	10.0	10.6
TUE	Total Unadjusted Error	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	-	7.8	17.0	LSB
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	-	8.0	32.0
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-	9.0	20.0
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	10.5	32.0
INL	Integral Non Linearity	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	-	+/-1.6	+/-3	LSB
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	-	+/-1.9	+/-3
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-	+/-1.5	+/-3
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	+/-3.2	+/-5
DNL	Differential Non Linearity	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	-	-0.8/+1	-1/+2	LSB
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	-	-0.7/+1.3	-1/+2.1
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-	-0.8/+1.1	-1/+3.3
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	-0.9/+1.3	-1/+3.2
Gain	Gain Error ⁽¹⁾	Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	+/-18	+/-57	mV
			Vddana=5.0V Vref=4.096V	-	+/-41	+/-100
			Vddana=3.0V Vref=Vddana	-	+/-17	+/-66
			Vddana=5.0V Vref=Vddana		+/-39	+/-81
TCg	Gain Drift	Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-250	-210	-170	μV/°C
Offset	Offset Error ⁽¹⁾	Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	+/-1.4	+/-11	mV
			Vddana=5.0V Vref=4.096V	-	+/-6	+/-18
			Vddana=3.0V Vref=Vddana	-	+/-2	+/-9
			Vddana=5.0V Vref=Vddana		+/-0.2	+/-23
Tco	Offset Drift	Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	20	80	120	μV/°C
SFDR		Spurious Free Dynamic Range	Fs = 1Msps / Fin = 14 kHz / Full range Input signal Vddana=5.0V Vref=Vddana	71	75	81	dB
SINAD		Signal to Noise and Distortion ratio		65	67	68
SNR		Signal to Noise ratio		67	68	69
THD				-77	-74	-70
		Noise RMS	External Reference voltage	-	0.5	2.0	mV

These values are based on characterization. These values are not covered by test limits in production.
For best ENOB with external reference, comparator offset cancellation is recommended to be turned off (SAMPCTRL.OFFCOMP=0).

Table 3. Single-Ended Mode⁽¹⁾
Symbol	Parameter	Conditions		Measurement			Unit
				Min	Typ	Max
ENOB⁽²⁾	Effective Number of bits	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	9.1	9.7	10.0	bits
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	9.1	9.4	9.8
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	9.1	9.7	9.9
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	9.0	9.2	9.6
TUE	Total Unadjusted Error	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	-	18.0	65.0	LSB
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	-	30.2	62.0
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-	18.4	60.0
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	30.4	61.0
INL	Integral Non Linearity	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	-	+/-2.4	+/-4	LSB
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	-	+/-3.7	+/-6
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-	+/-2.2	+/-4
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	+/-4.1	+/-6
DNL	Differential Non Linearity	Fadc = 500 ksps	Vddana=5.0V Vref=Vddana	-	-0.8/+1.1	-1/+3.8	LSB
		Fadc = 500 ksps	Vddana=2.7V Vref=2.0V	-	-0.8/+1.1	-1/+1.7
		Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-	-0.8/+1	-1/+2
		Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	-1/+1.1	-1/+2.4
Gain	Gain Error ⁽¹⁾	Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	+/-13	+/-28	mV
			Vddana=5.0V Vref=4.096V	-	+/-26	+/-52
			Vddana=3.0V Vref=Vddana	-	+/-14	+/-24
			Vddana=5.0V Vref=Vddana		+/-22	+/-42
TCg	Gain Drift	Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	-170	-140	-80	uV/°C
Offset	Offset Error ⁽¹⁾	Fadc = 1 Msps	Vddana=2.7V Vref=2.0V	-	+/-2.2	+/-21	mV
			Vddana=5.0V Vref=4.096V	-	+/-2.3	+/-61
			Vddana=3.0V Vref=Vddana	-	+/-15	+/-42
			Vddana=5.0V Vref=Vddana		+/-31	+/-80
Tco	Offset Drift	Fadc = 1 Msps	Vddana=5.0V Vref=Vddana	160	180	210	μV/°C
SFDR		Spurious Free Dynamic Range	Fs = 1Msps / Fin = 14 kHz / Full range Input signal Vddana=5.0V Vref=Vddana	69	71	73	dB
SINAD		Signal to Noise and Distortion ratio		57	60	61
SNR		Signal to Noise ratio		57	61	61
THD				-72	-70	-66
		Noise RMS	External Reference voltage	-	0.7	2.0	mV

These values are based on characterization. These values are not covered by test limits in production.
For best ENOB with external reference, comparator offset cancellation is recommended to be turned off (SAMPCTRL.OFFCOMP=0).

Table 4. Power Consumption⁽¹⁾
Symbol	Parameters	Conditions	Ta	Typ.	Max	Units
IDD VDDANA	Differential mode	fs = 1 Msps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref= 5.5V	Max 85°C Typ 25°C	905	1021	μA
		fs = 1 Msps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref= 5.5V		1062	1184
		fs = 10 ksps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref= 5.5V		381	460
		fs = 10 ksps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref= 5.5V		525	643
	Single Ended mode	fs = 1 Msps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref=5.5V	Max 85°C Typ 25°C	984	1077	μA
		fs = 1 Msps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref=5.5V		1103	1237
		fs = 10 ksps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref= 5.5V		437	528
		fs = 10 ksps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA=Vref= 5.5V		553	675

These are based on characterization.