| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| Access | |||||||
| Reset | |||||||
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| LEVEL[5:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PSEL[3:0] | ACTCFG | ||||||
| AccessR/W | R/W | R/W | R/W | R/W | |||
| Reset0 | 0 | 0 | 0 | 0 | |||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RUNSTDBY | STDBYCFG | ACTION[1:0] | HYST | ENABLE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |
BODCORE Threshold Level
This field sets the triggering voltage threshold for the BODCORE.
These bits are loaded from NVM User Row at start-up.
This field is not synchronized.
Prescaler Select
Selects the prescaler divide-by output for the BODCORE Sampling mode. The input clock comes from the OSCULP32K 1KHz output.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV2 | Divide clock by 2 |
| 0x1 | DIV4 | Divide clock by 4 |
| 0x2 | DIV8 | Divide clock by 8 |
| 0x3 | DIV16 | Divide clock by 16 |
| 0x4 | DIV32 | Divide clock by 32 |
| 0x5 | DIV64 | Divide clock by 64 |
| 0x6 | DIV128 | Divide clock by 128 |
| 0x7 | DIV256 | Divide clock by 256 |
| 0x8 | DIV512 | Divide clock by 512 |
| 0x9 | DIV1024 | Divide clock by 1024 |
| 0xA | DIV2048 | Divide clock by 2048 |
| 0xB | DIV4096 | Divide clock by 4096 |
| 0xC | DIV8192 | Divide clock by 8192 |
| 0xD | DIV16384 | Divide clock by 16384 |
| 0xE | DIV32768 | Divide clock by 32768 |
| 0xF | DIV65536 | Divide clock by 65536 |
BODCORE Configuration in Active Sleep Mode
This field is not synchronized.
| Value | Description |
|---|---|
| 0 | In active mode, the BODCORE operates in continuous mode. |
| 1 | In active mode, the BODCORE operates in sampling mode. |
Run in Standby
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | In standby sleep mode, the BODCORE is disabled. |
| 1 | In standby sleep mode, the BODCORE is enabled. |
BODCORE Configuration in Standby Sleep Mode
If the RUNSTDBY bit is set to 1, the STDBYCFG bit sets the BODCORE configuration in standby sleep mode.
This field is not synchronized.
| Value | Description |
|---|---|
| 0 | In standby sleep mode, the BODCORE is enabled and configured in continuous mode. |
| 1 | In standby sleep mode, the BODCORE is enabled and configured in sampling mode. |
BODCORE Action
These bits are used to select the BODCORE action when the supply voltage crosses below the BODCORE threshold.
These bits are loaded from NVM User Row at start-up.
This field is not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No action. |
| 0x1 | RESET | The BODCORE generates a reset. |
| 0x2 | INT | The BODCORE generates an interrupt. |
| 0x3 | - | Reserved |
Hysteresis
This bit indicates whether hysteresis is enabled for the BODCORE threshold voltage:
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | No hysteresis. |
| 1 | Hysteresis enabled. |
Enable
This bit is loaded from NVM User Row at start-up.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | BODCORE is disabled. |
| 1 | BODCORE is enabled. |