BUSYCH

Name:: BUSYCH
Offset:: 0x28
Reset:: 0x00000000
Access:: -

Bit31	30	29	28	27	26	25	24

Access
Reset
Bit23	22	21	20	19	18	17	16

Access
Reset
Bit15	14	13	12	11	10	9	8

Access
Reset
Bit7	6	5	4	3	2	1	0
		BUSYCH5	BUSYCH4	BUSYCH3	BUSYCH2	BUSYCH1	BUSYCH0
Access		R	R	R	R	R	R
Reset		0	0	0	0	0	0

Bits 5:0 – BUSYCHn: Busy Channel n [x=5..0]

Busy Channel n [x=5..0]

This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled.

This bit is set when DMA channel n starts a DMA transfer.