| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| Access | |||||||
| Reset | |||||||
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Access | |||||||
| Reset | |||||||
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Access | |||||||
| Reset | |||||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTRLB | ENABLE | SWRST | |||||
| Access | R | R | R | ||||
| Reset | 0 | 0 | 0 |
CTRLB Synchronization Busy
Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated.
| Value | Description |
|---|---|
| 0 | CTRLB synchronization is not busy. |
| 1 | CTRLB synchronization is busy. |
SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated.
| Value | Description |
|---|---|
| 0 | Enable synchronization is not busy. |
| 1 | Enable synchronization is busy. |
Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
| Value | Description |
|---|---|
| 0 | SWRST synchronization is not busy. |
| 1 | SWRST synchronization is busy. |