Clock Generation (Standard-mode, Fast-mode and Fast-mode Plus Transfers)

In I²C Sm, Fm, and Fm+ mode, the Master clock (SCL) frequency is determined as described in this section:

The low (T_LOW) and high (T_HIGH) times are determined by the Baud Rate register (BAUD), while the rise (T_RISE) and fall (T_FALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, T_FALLwill be considered as part of T_LOW. Likewise, T_RISEwill be in a state between T_LOW and T_HIGH until a high state has been detected.

Figure 1. SCL Timing

The following parameters are timed using the SCL low time period T_LOW. This comes from the Master Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.

T_LOW – Low period of SCL clock
T_SU;STO– Set-up time for stop condition
T_BUF – Bus free time between stop and start conditions
T_HD;STA – Hold time (repeated) start condition
T_SU;STA – Set-up time for repeated start condition
T_HIGH is timed using the SCL high time count from BAUD.BAUD
T_RISE is determined by the bus impedance; for internal pull-ups. Refer to Electrical Characteristics.
T_FALLis determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer to Electrical Characteristics for details.

The SCL frequency is given by:

fSCL=1TLOW+THIGH+TRISE

When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency:

fSCL=fGCLK10⁢+ 2BAUD+fGCLK⋅TRISE

When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:

fSCL=fGCLK10⁢+ BAUD+BAUDLOW+fGCLK⋅TRISE

The following formulas can determine the SCL T_LOW and T_HIGH times:

TLOW=BAUDLOW+5fGCLK

THIGH=BAUD+5fGCLK

Note: The I²C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero.

Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA write and IF clear must be controlled by software.

Note: When timing is controlled by user, the Smart Mode cannot be enabled.

Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)