| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLKRDY | LOCK | ||||||
| Access | R | R | |||||
| Reset | 0 | 0 |
Output Clock Ready
| Value | Description |
|---|---|
| 0 | The DPLL output clock is off. |
| 1 | The DPLL output clock in on. |
DPLL Lock status bit
| Value | Description |
|---|---|
| 0 | The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the target frequency. |
| 1 | The DPLL Lock signal is asserted when the desired frequency is reached. |