DATA

Name:: DATA
Offset:: 0x28
Reset:: 0x0000
Access:: –

Bit15	14	13	12	11	10	9	8
							DATA[8:8]
Access							R/W
Reset							0
Bit7	6	5	4	3	2	1	0
DATA[7:0]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0

Bits 8:0 – DATA[8:0]: Data

Data

Reading these bits will return the contents of the receive data buffer. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set.

Writing these bits will write the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.