Digital Phase Locked Loop (DPLL) Characteristics

Table 1. Fractional Digital Phase Locked Loop Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN⁽¹⁾	Input frequency		32		2000	KHz
f_OUT⁽¹⁾	Output frequency		48		96	MHz
Jp⁽²⁾	Period jitter (Peak-Peak value)	f_IN= 32 kHz, f_OUT= 48 MHz	-	1.8	4.0	%
		f_IN= 32 kHz, f_OUT= 96 MHz	-	4.2	19.0
		f_IN= 2 MHz, f_OUT= 48 MHz	-	2.0	4.0
		f_IN= 2 MHz, f_OUT= 96 MHz	-	3.7	9.0
t_LOCK⁽²⁾	Lock Time	After startup, time to get lock signal. f_IN= 32 kHz, f_OUT= 96 MHz	-	1.1	1.5	ms
t_LOCK⁽²⁾	Lock Time	After startup, time to get lock signal. f_IN= 2 MHz, f_OUT= 96 MHz	-	25	35	μs
Duty	Duty cycle		-	50	-	%

These values are based on simulation. These values are not covered by test limits in production or characterization.
These values are based on characterization.

Table 2. Power Consumption⁽¹⁾
Symbol	Parameters	Conditions	Ta	Typ.	Max	Units
IDD	Current Consumption	Ck=48MHz, VDD=5.0V	Max 85°C Typ 25°C	-	612	µA
IDD	Current Consumption	Ck=96MHz, VDD=5.0V	Max 85°C Typ 25°C	-	970	µA