Physical Memory Map

The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follow:

Table 1. SAM C20 Physical Memory Map⁽¹⁾
Memory	Start address	Size	Size	Size	Size
Memory	Start address	SAM C20x18	SAM C20x17	SAM C20x16	SAM C20x15
Embedded Flash	0x00000000	256Kbytes	128Kbytes	64Kbytes	32Kbytes
Embedded RWW section	0x00400000	8Kbytes	4Kbytes	2Kbytes	1Kbytes
Embedded high-speed SRAM	0x20000000	32Kbytes	16Kbytes	8Kbytes	4Kbytes
AHB-APB Bridge A	0x40000000	64Kbytes	64Kbytes	64Kbytes	64Kbytes
AHB-APB Bridge B	0x41000000	64Kbytes	64Kbytes	64Kbytes	64Kbytes
AHB-APB Bridge C	0x42000000	64Kbytes	64Kbytes	64Kbytes	64Kbytes
AHB DIVAS	0x48000000	64Kbytes	64Kbytes	64Kbytes	64Kbytes
IOBUS	0x60000000	64Kbytes	64Kbytes	64Kbytes	64Kbytes

Note: 1. x = G, J or E.

Table 2. Flash Memory Parameters⁽¹⁾
Device	Flash size (FLASH_PM)	Number of pages (FLASH_P)	Page size (FLASH_W)
SAM C20x18	256Kbytes	4096	64 bytes
SAM C20x17	128Kbytes	2046	64 bytes
SAM C20x16	64Kbytes	1024	64 bytes
SAM C20x15	32Kbytes	512	64 bytes

Note: 1. x = G, J or E .

Table 3. RWW Section Parameters⁽¹⁾
Device	Flash size (FLASH_PM)	Number of pages (FLASH_P)	Page size (FLASH_W)
SAM C20x18	8Kbytes	128	64 bytes
SAM C20x17	4Kbytes	64	64 bytes
SAM C20x16	2Kbytes	32	64 bytes
SAM C20x15	1Kbytes	16	64 bytes

Note: 1. x = G, J or E .