| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| Access | |||||||
| Reset | |||||||
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Access | |||||||
| Reset | |||||||
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Access | |||||||
| Reset | |||||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HMATRIXHS | NVMCTRL | DSU | PORT | ||||
| Access | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 1 | 1 |
HMATRIXHS APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the HMATRIXHS is stopped |
| 1 | The APBB clock for the HMATRIXHS is enabled |
NVMCTRL APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the NVMCTRL is stopped |
| 1 | The APBB clock for the NVMCTRL is enabled |
DSU APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the DSU is stopped |
| 1 | The APBB clock for the DSU is enabled |
PORT APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the PORT is stopped. |
| 1 | The APBB clock for the PORT is enabled. |