Contents

Introduction Features Description Configuration Summary Ordering Information SAM C20E SAM C20G SAM C20J Device Identification Block Diagram Pinout SAM C20E QFN32 / TQFP32 SAM C20G QFN48 / TQFP48 SAM C20J QFN64 / TQFP64 WLCSP56 Signal Descriptions List I/O Multiplexing and Considerations Multiplexed Signals Other Functions Oscillator Pinout Serial Wire Debug Interface Pinout SERCOM I2C Pins GPIO Clusters TCC Configurations Power Supply and Start-Up Considerations Power Domain Overview Power Supply Considerations Power Supplies Voltage Regulator Typical Powering Schematics Power-Up Sequence Minimum Rise Rate Maximum Rise Rate Power-Up Starting of Clocks I/O Pins Fetching of Initial Instructions Power-On Reset and Brown-Out Detector Power-On Reset on VDDIN Power-On Reset on VDDIO Brown-Out Detector on VDDIN Brown-Out Detector on VDDCORE Product Mapping Memories Embedded Memories Physical Memory Map NVM User Row Mapping NVM Software Calibration Area Mapping Serial Number Processor and Architecture Cortex M0+ Processor Cortex M0+ Configuration Cortex-M0+ Peripherals Cortex-M0+ Address Map I/O Interface Overview Description Nested Vector Interrupt Controller Overview Interrupt Line Mapping Micro Trace Buffer Features Overview High-Speed Bus System Features Configuration SRAM Quality of Service PAC - Peripheral Access Controller Overview Features Block Diagram Product Dependencies IO Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Functional Description Principle of Operation Basic Operation Initialization Enabling and Resetting Operations Peripheral Access Errors Write Access Protection Management Write Access Protection Management Errors AHB Slave Bus Errors Generating Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description WRCTRL EVCTRL INTENCLR INTENSET INTFLAGAHB INTFLAGA INTFLAGB INTFLAGC STATUSA STATUSB STATUSC Peripherals Configuration Summary DSU - Device Service Unit Overview Features Block Diagram Signal Description Product Dependencies IO Lines Power Management Clocks DMA Interrupts Events Register Access Protection Analog Connections Debug Operation Principle of Operation CPU Reset Extension Debugger Probe Detection Cold Plugging Hot Plugging Chip Erase Programming Intellectual Property Protection Device Identification CoreSight Identification Chip Identification Method Functional Description Principle of Operation Basic Operation Initialization Operation From a Debug Adapter Operation From the CPU 32-bit Cyclic Redundancy Check CRC32 Starting CRC32 Calculation Interpreting the Results Debug Communication Channels Testing of On-Board Memories MBIST System Services Availability when Accessed Externally Register Summary Register Description CTRL STATUSA STATUSB ADDR LENGTH DATA DCC0 DCC1 DID ENTRY0 ENTRY1 END MEMTYPE PID4 PID0 PID1 PID2 PID3 CID0 CID1 CID2 CID3 DIVAS – Divide and Square Root Accelerator Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections CPU Local Bus Functional Description Principle of Operation Basic Operation Initialization Performing Division Operand Size Signed Division Divide By Zero Leading Zero Optimization Unsigned Square Root Register Summary Register Description CTRLA STATUS DIVIDEND DIVISOR RESULT REMAINDER SQRNUM Clock System Clock Distribution Synchronous and Asynchronous Clocks Register Synchronization Overview General Write-Synchronization General Read-Synchronization Completion of Synchronization Enable Write-Synchronization Software Reset Write-Synchronization Synchronization Delay Enabling a Peripheral On-demand, Clock Requests Power Consumption vs. Speed Clocks after Reset GCLK - Generic Clock Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Generic Clock Generator Enabling a Generator Disabling a Generator Selecting a Clock Source for the Generator Changing the Clock Frequency Duty Cycle External Clock Peripheral Clock Enabling a Peripheral Clock Disabling a Peripheral Clock Selecting the Clock Source for a Peripheral Configuration Lock Additional Features Peripheral Clock Enable after Reset Sleep Mode Operation SleepWalking Minimize Power Consumption in Standby Entering Standby Mode Synchronization Register Summary Register Description CTRLA SYNCBUSY GENCTRLn PCHCTRLmn MCLK – Main Clock Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks Main Clock CPU Clock APBx and AHBx Clock Clock Domains DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Selecting the Main Clock Source Selecting the Synchronous Clock Division Ratio Clock Ready Flag Peripheral Clock Masking DMA Operation Interrupts Events Sleep Mode Operation Register Summary - MCLK Register Description CTRLA INTENCLR INTENSET INTFLAG CPUDIV AHBMASK APBAMASK APBBMASK APBCMASK RSTC – Reset Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Reset Causes and Effects Additional Features DMA Operation Interrupts Events Sleep Mode Operation Register Summary Register Description RCAUSE PM – Power Manager Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Terminology Sleep Modes Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Sleep Mode Controller IDLE Mode STANDBY Mode Advanced Features RAM Automatic Low Power Mode Regulator Automatic Low Power Mode DMA Operation Interrupts Events Sleep Mode Operation Register Summary Register Description SLEEPCFG STDBYCFG OSCCTRL – Oscillators Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation External Multipurpose Crystal Oscillator (XOSC) Operation Clock Failure Detection Operation 48MHz Internal Oscillator (OSC48M) Operation Digital Phase Locked Loop (DPLL) Operation Basic Operation Initialization, Enabling, Disabling, and Resetting Reference Clock Switching Output Clock Prescaler Loop Divider Ratio Updates Digital Filter Selection DMA Operation Interrupts Events Synchronization Register Summary Register Description INTENCLR INTENSET INTFLAG STATUS XOSCCTRL CFDPRESC EVCTRL OSC48MCTRL OSC48MDIV OSC48MSTUP OSC48MSYNCBUSY DPLLCTRLA DPLLRATIO DPLLCTRLB DPLLPRESC DPLLSYNCBUSY DPLLSTATUS CAL48M OSC32KCTRL – 32KHz Oscillators Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks Interrupts Events Debug Operation Register Access Protection Analog Connections Calibration Functional Description Principle of Operation 32KHz External Crystal Oscillator (XOSC32K) Operation Clock Failure Detection Operation 32KHz Internal Oscillator (OSC32K) Operation 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation Watchdog Timer Clock Selection Real-Time Counter Clock Selection Interrupts Events Register Summary Register Description INTENCLR INTENSET INTFLAG STATUS RTCCTRL XOSC32K CFDCTRL EVCTRL OSC32K OSCULP32K SUPC – Supply Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Voltage Regulator System Operation Enabling, Disabling, and Resetting Initialization Sleep Mode Operation Voltage Reference System Operation Initialization Enabling, Disabling, and Resetting Selecting a Voltage Reference Sleep Mode Operation Brown-Out Detectors Initialization Enabling, Disabling, and Resetting VDD Brown-Out Detector (BODVDD) VDDCORE Brown-Out Detector (BODCORE) Continuous Mode Sampling Mode Hysteresis Sleep Mode Operation Standby Mode Interrupts Synchronization Register Summary Register Description INTENCLR INTENSET INTFLAG STATUS BODVDD VREG VREF WDT – Watchdog Timer Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Configurable Reset Values Enabling, Disabling, and Resetting Normal Mode Window Mode DMA Operation Interrupts Events Sleep Mode Operation Synchronization Additional Features Always-On Mode Early Warning Register Summary Register Description CTRLA CONFIG EWCTRL INTENCLR INTENSET INTFLAG SYNCBUSY CLEAR RTC – Real-Time Counter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting 32-Bit Counter (Mode 0) 16-Bit Counter (Mode 1) Clock/Calendar (Mode 2) DMA Operation Interrupts Events Sleep Mode Operation Synchronization Additional Features Periodic Intervals Frequency Correction Register Summary - COUNT32 Register Description - COUNT32 CTRLA EVCTRL INTENCLR INTENSET INTFLAG DBGCTRL SYNCBUSY FREQCORR COUNT COMP0 Register Summary - COUNT16 Register Description - COUNT16 CTRLA EVCTRL INTENCLR INTENSET INTFLAG DBGCTRL SYNCBUSY FREQCORR COUNT PER COMPn Register Summary - CLOCK Register Description - CLOCK CTRLA EVCTRL INTENCLR INTENSET INTFLAG DBGCTRL SYNCBUSY FREQCORR CLOCK ALARM MASK DMAC – Direct Memory Access Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation DMA CRC Basic Operation Initialization Enabling, Disabling, and Resetting Transfer Descriptors Arbitration Data Transmission Transfer Triggers and Actions Addressing Error Handling Additional Features Linked Descriptors Adding Descriptor to the End of a List Modifying a Descriptor in a List Adding a Descriptor Between Existing Descriptors Channel Suspend Channel Resume and Next Suspend Skip Event Input Actions Event Output Selection Aborting Transfers CRC Operation DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRL CRCCTRL CRCDATAIN CRCCHKSUM CRCSTATUS DBGCTRL QOSCTRL SWTRIGCTRL PRICTRL0 INTPEND INTSTATUS BUSYCH PENDCH ACTIVE BASEADDR WRBADDR CHID CHCTRLA CHCTRLB CHINTENCLR CHINTENSET CHINTFLAG CHSTATUS Register Summary - SRAM Register Description - SRAM BTCTRL BTCNT SRCADDR DSTADDR DESCADDR EIC – External Interrupt Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting External Pin Processing Additional Features Non-Maskable Interrupt (NMI) Asynchronous Edge Detection Mode DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA NMICTRL NMIFLAG SYNCBUSY EVCTRL INTENCLR INTENSET INTFLAG ASYNCH CONFIG0, CONFIG1, CONFIG2, CONFIG3 NVMCTRL – Non-Volatile Memory Controller Overview Features Block Diagram Signal Description Product Dependencies Power Management Clocks Interrupts Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Initialization Memory Organization Region Lock Bits Command and Data Interface NVM Read RWWEE Read NVM Write Procedure for Manual Page Writes (CTRLB.MANW=1) Procedure for Automatic Page Writes (CTRLB.MANW=0) Page Buffer Clear Erase Row Procedure for Erase Row Lock and Unlock Region Set and Clear Power Reduction Mode NVM User Configuration Security Bit Cache Register Summary Register Description CTRLA CTRLB PARAM INTENCLR INTENSET INTFLAG STATUS ADDR LOCK PBLDATA0 PBLDATA1 PORT - I/O Pin Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections CPU Local Bus Functional Description Principle of Operation Basic Operation Initialization Operation I/O Pin Configuration Pin Configurations Summary Input Configuration Totem-Pole Output Digital Functionality Disabled Events PORT Access Priority Register Summary Register Description DIR DIRCLR DIRSET DIRTGL OUT OUTCLR OUTSET OUTTGL IN CTRL WRCONFIG EVCTRL PMUXn PINCFGn EVSYS – Event System Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting User Multiplexer Setup Event System Channel Event Generators Channel Path Edge Detection Event Latency The Overrun Channel n Interrupt The Event Detected Channel n Interrupt Channel Status Software Event Interrupts Sleep Mode Operation Register Summary Common Registers CHANNELn USERm Register Description CTRLA CHSTATUS INTENCLR INTENSET INTFLAG SWEVT CHANNELn USERm SERCOM – Serial Communication Interface Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Clock Generation – Baud-Rate Generator Asynchronous Arithmetic Mode BAUD Value Selection Additional Features Address Match and Mask Address With Mask Two Unique Addresses Address Range DMA Operation Interrupts Events Sleep Mode Operation Synchronization SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter Overview USART Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Clock Generation and Selection Synchronous Clock Operation Data Register Data Transmission Disabling the Transmitter Data Reception Disabling the Receiver Error Bits Asynchronous Data Reception Asynchronous Operational Range Additional Features Parity Hardware Handshaking IrDA Modulation and Demodulation Break Character Detection and Auto-Baud LIN Master RS485 Collision Detection Loop-Back Mode Start-of-Frame Detection Sample Adjustment DMA, Interrupts and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLB CTRLC BAUD RXPL INTENCLR INTENSET INTFLAG STATUS SYNCBUSY DATA DBGCTRL SERCOM SPI – SERCOM Serial Peripheral Interface Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Clock Generation Data Register SPI Transfer Modes Transferring Data Master Slave Receiver Error Bit Additional Features Address Recognition Preloading of the Slave Shift Register Master with Several Slaves Loop-Back Mode Hardware Controlled SS Slave Select Low Detection DMA, Interrupts, and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLB BAUD INTENCLR INTENSET INTFLAG STATUS SYNCBUSY ADDR DATA DBGCTRL SERCOM I2C – SERCOM Inter-Integrated Circuit Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting I2C Bus State Logic I2C Master Operation Master Clock Generation Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) Master Clock Generation (High-Speed Mode) Transmitting Address Packets Transmitting Data Packets Receiving Data Packets (SCLSM=0) Receiving Data Packets (SCLSM=1) High-Speed Mode 10-Bit Addressing I2C Slave Operation Receiving Address Packets (SCLSM=0) Receiving Address Packets (SCLSM=1) Receiving and Transmitting Data Packets High-Speed Mode 10-Bit Addressing PMBus Group Command Additional Features SMBus Smart Mode 4-Wire Mode Quick Command DMA, Interrupts and Events DMA Operation Slave DMA Master DMA Interrupts Events Sleep Mode Operation Synchronization Register Summary - I2C Slave Register Description - I2C Slave CTRLA CTRLB INTENCLR INTENSET INTFLAG STATUS SYNCBUSY ADDR DATA Register Summary - I2C Master Register Description - I2C Master CTRLA CTRLB BAUD INTENCLR INTENSET INTFLAG STATUS SYNCBUSY ADDR DATA DBGCTRL TC – Timer/Counter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Prescaler Selection Counter Mode Counter Operations Stop Command and Event Action Re-Trigger Command and Event Action Count Event Action Start Event Action Compare Operations Waveform Output Operations Double Buffering Capture Operations Event Capture Action Period and Pulse-Width (PPW) Capture Action Pulse-Width Capture Action Additional Features One-Shot Operation Time-Stamp Capture DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLBCLR CTRLBSET EVCTRL INTENCLR INTENSET INTFLAG STATUS WAVE DRVCTRL DBGCTRL SYNCBUSY COUNT COUNT COUNT PER CCx CCx CCx PERBUF CCBUFx CCBUFx CCBUFx TCC – Timer/Counter for Control Applications Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Prescaler Selection Counter Operation Compare Operations Waveform Output Generation Operations Normal Frequency (NFRQ) Match Frequency (MFRQ) Normal Pulse-Width Modulation (NPWM) Single-Slope PWM Operation Dual-Slope PWM Generation Dual-Slope Critical PWM Generation Output Polarity Double Buffering Capture Operations Additional Features One-Shot Operation Circular Buffer Dithering Operation Ramp Operations Recoverable Faults Non-Recoverable Faults Waveform Extension WaveformGenerationinRAMP1modeWithRestartAction Master/Slave Operation DMA, Interrupts, and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLBCLR CTRLBSET SYNCBUSY FCTRLA, FCTRLB WEXCTRL DRVCTRL DBGCTRL EVCTRL INTENCLR INTENSET INTFLAG STATUS COUNT PATT WAVE PER CCn PATTB WAVEB PERB CCBn CCL – Configurable Custom Logic Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Lookup Table Logic Truth Table Inputs Selection Filter Edge Detector Sequential Logic Events Sleep Mode Operation Register Summary Register Description CTRL SEQCTRLn LUTCTRLn ADC – Analog-to-Digital Converter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Calibration Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Operation Prescaler Selection Reference Configuration ADC Resolution Differential and Single-Ended Conversions Conversion Timing and Sampling Rate Accumulation Averaging Oversampling and Decimation Automatic Sequences Window Monitor Offset and Gain Correction Additional Features Rail-to-Rail Operation DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLB REFCTRL EVCTRL INTENCLR INTENSET INTFLAG SEQSTATUS INPUTCTRL CTRLC AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR SWTRIG DBGCTRL SYNCBUSY RESULT SEQCTRL CALIB AC – Analog Comparators Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Comparator Configuration Starting a Comparison Continuous Measurement Single-Shot Selecting Comparator Inputs Window Operation VDD Scaler Input Hysteresis Propagation Delay vs. Power Consumption Filtering Comparator Output Offset Compensation DMA Operation Interrupts Events Sleep Mode Operation Continuous Measurement during Sleep Single-Shot Measurement during Sleep Synchronization Register Summary Register Description CTRLA CTRLB EVCTRL INTENCLR INTENSET INTFLAG STATUSA STATUSB DBGCTRL WINCTRL SCALERn COMPCTRLn SYNCBUSY PTC - Peripheral Touch Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Mutual-capacitance Sensor Arrangement Self-capacitance Sensor Arrangement Clocks Functional Description FREQM – Frequency Meter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Measurement DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLB CFGA INTENCLR INTENSET INTFLAG STATUS SYNCBUSY VALUE Electrical Characteristics 85°C Disclaimer Absolute Maximum Ratings General Operating Ratings Injection Current Supply Characteristics Maximum Clock Frequencies Power Consumption Wake-Up Time I/O Pin Characteristics Analog Characteristics POR - Power On Reset Characteristics Brown Out Detectors Characteristics Voltage Regulator Characteristics Analog-to-Digital Converter (ADC) Characteristics Analog Comparator Characteristics Voltage Reference Characteristics NVM Characteristics Oscillator Characteristics Crystal Oscillator (XOSC) Characteristics Digital Clock Characteristics Crystal Oscillator Characteristics External 32 kHz Crystal Oscillator (XOSC32K) Characteristics Digital Clock Characteristics Crystal Oscillator Characteristics Digital Phase Locked Loop (DPLL) Characteristics 32.768kHz Internal oscillator (OSC32K) Characteristics Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics 48MHz RC Oscillator (OSC48M) Characteristics Timing Characteristics SERCOM in SPI Mode Timing External Reset Electrical Characteristics 105°C Disclaimer General Operating Ratings Power Consumption Analog Characteristics Brown Out Detector Characteristics - BODVDD Analog-to-Digital Converter (ADC) Characteristics Analog Comparator (AC) Characteristics NVM Characteristics Oscillator Characteristics Crystal Oscillator (XOSC) Characteristics External 32kHz Crystal Oscillator (XOSC32K) Characteristics Digital Phase Locked Loop (DPLL) Characteristics 32.768kHz Internal Oscillator (OSC32K) Characteristics Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics 48MHz RC Oscillator (OSC48M) Characteristics Packaging Information Thermal Considerations Thermal Resistance Data Junction Temperature Package Drawings 64 pin TQFP 64 pin QFN 56-Ball WLCSP 48 pin TQFP 48 pin QFN 32 pin TQFP 32 pin QFN Soldering Profile Schematic Checklist Introduction Operation in Noisy Environment Power Supply Power Supply Connections External Analog Reference Connections External Reset Circuit Unused or Unconnected Pins Clocks and Crystal Oscillators External Clock Source Crystal Oscillator External Real Time Oscillator Calculating the Correct Crystal Decoupling Capacitor Programming and Debug Ports Cortex Debug Connector (10-pin) 10-pin JTAGICE3 Compatible Serial Wire Debug Interface 20-pin IDC JTAG Connector Errata Revision History Rev J - 11/2016 Rev I - 09/2016 Rev H - 05/2016 Rev G - 04/2015 Rev F - 02/2015 Rev E - 12/2015 Rev D - 09/2015 Rev C - 09/2015 Rev B - 06/2015 Rev A - 04/2015 Legal Disclaimer