Inside an ADC, the sample and hold circuit of the ADC contains a
resistance-capacitance (RADC and CADC) pair in a low pass filter
arrangement. The CADC is also called as sampling capacitor. Whenever an ADC
start conversion signal is issued, the sampling switches between the RADC –
CADC pair is closed so that the analog input voltage charges the sampling
capacitor through the resistance RADC.
The following figure depicts the equivalent circuit of
an
ADC system.
Figure 1. Equivalent Circuit of
an
ADC
System
The input impedance of the ADC is the combination of RADC and the
impedance of the capacitor. As the sampling capacitor gets charged to the input voltage,
the current through RADC reduces and ends up with a minimum value when
voltage across the sampling capacitor equals the input voltage. So the minimum input
impedance of the ADC equals RADC.
In the source side, the ideal source voltage is
subject to some resistance called the source resistance (R
SRC) and some
capacitance called source capacitance (C
SRC) present in the source module.
Because of the presence of R
SRC, the current entering the sample and hold
circuit reduces. So this reduction in current increases the time to charge the sampling
capacitance thereby reducing the speed of the ADC. Also the presence of C
SRC
makes the source to first charge it completely before charging the sampling capacitor.
This reduces the accuracy of the ADC since the sampling capacitor may not be completely
charged.
Note:
- RADC and
CADC are
a
part of the ADC
specification.
Refer
the
device
datasheet
for more information.
- RSRC and
CSRC directly affects the operating speed and accuracy of ADC
module. In the practical applications, RSRC and CSRC
of the input signal
must
be
considered
while selecting the ADC parameters.