TCNT0H and TCNT0L are combined into TCNT0. It also means TCNT0L[7:0] is TCNT0[7:0].

The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Registers for details.

Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a compare match between TCNT0 and one of the OCR0x Registers.

Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock for all compare units.