Output Compare Register 0 B Low byte
Name:
OCR0BL
Offset:
0x24
Reset:
0x00
Access:
-
Bit76543210
(OCR0B[7:0]) OCR0BL
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 7:0 – (OCR0B[7:0]) OCR0BL[7:0]: Output Compare 0 B Low byte

Output Compare 0 B Low byte

OCR0BH and OCR0BL are combined into OCR0B. It means OCR0BL[7:0] is OCR0B[7:0].

The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers”.