Generating Two PWM Signals in Split Mode

A TCA instance can be split in two completely independent 8-bit timers. This feature provides a high degree of flexibility, being extremely helpful in waveform generation applications. Except in the cases where high accuracy signals are required, most of the applications can be designed using 8-bit signal generators and the possibility of adding one more generator to the design can be a big advantage. Though, there are more limitations in the Split mode than the Counter registers dimension. The most important one is that both 8-bit timers have only the down-count option, so the Dual-Slope PWM mode becomes unavailable. Also, the buffering scheme cannot be used, and the timers can no longer count events, only clock ticks. Moreover, there are no interrupts or flags for high-byte Compare registers. Regardless of these limitations, the Split mode can be really attractive when there is a need for a high number of timers. The block diagram of the TCA in Split mode is provided below.

Figure 1. Timer/Counter Block Diagram Spit Mode

This mode will be put forward by generating two PWM signals with different frequencies and different duty cycles.

1.The TCA corresponding register in Port Multiplexer can be set to rout the module outputs to different ports, in this case, Port A is chosen, which is also the default port.
```
PORTMUX.TCAROUTEA = PORTMUX_TCA0_PORTA_gc;
```
Figure 2. TCAROUTEA Register
2.Split mode is enabled by setting the corresponding bit in CTRLD register.
```
TCA0.SPLIT.CTRLD = TCA_SPLIT_SPLITM_bm;
```
Figure 3. CTRLD Register
3.The CTRLB register contains the Enable bits of the compare channels. In this example, channel 0 of the lower byte of the timer and channel 0 of the higher byte of the timer are used.
```
TCA0.SPLIT.CTRLB = TCA_SPLIT_HCMP0EN_bm
                         | TCA_SPLIT_LCMP0EN_bm;
```
Figure 4. CTRLB Register - Split Mode
4.In this mode, the Period register and the Compare registers are split in half. Each half of the Period register determines the frequency of the respective PWM signal. Using the desired frequency value, the Period register value can be deduced from the following formula:

fss⁢ PWM=fCLK(Hz)TCAprescaler⁢ ⁢×(TCAperiod⁢ +1)

Considering the targeted values for this example,

TCAperiod⁢ ⁢1=fCLK(Hz)TCAprescaler⁢ ×fss⁢ PWM1(Hz)−1=333333316×1000−1≅207=0xCF

TCAperiod⁢ 2=fCLK(Hz)TCAprescaler×fss⁢PWM2(Hz)−1=333333316×3000−1≅68=0x44

This translates to the following lines of code:
```
TCA0.SPLIT.LPER = 0xCF;

TCA0.SPLIT.HPER = 0x44;
```
5.Each half of the Compare registers determines the duty cycle of the respective PWM signal.
```
TCA0.SPLIT.LCMP0 = 0x68;

TCA0.SPLIT.HCMP0 = 0x11;
```
6.From the CTRLA register the prescaler is set to 16. To start the counter, the user must set the Enable bit in the same register.
```
TCA0.SPLIT.CTRLA = TCA_SPLIT_CLKSEL_DIV16_gc
                        | TCA_SPLIT_ENABLE_bm;
```
7.The initialization code provided illustrates a simple way of configuring the TCA in Split mode, but some mentions must be made. The Single Slope PWM mode is the only Waveform Generation mode available. Also, it is recommended to stop the timer and to do a hard Reset before switching from Normal mode to Split mode. An example is provided below. To stop the counter, the Enable bit in the CTRLA register must be cleared. Then, in the Command bit field of the CTRLESET register, the user will write the code of the hard Reset command.
```
void TCA0_hardReset(void)
{
    TCA0.SINGLE.CTRLA &= ~(TCA_SINGLE_ENABLE_bm);  
   
    TCA0.SINGLE.CTRLESET = TCA_SINGLE_CMD_RESET_gc; 
}
```
8.Then, the pins 0 and 3 of Port A (PA0 and PA3) are set as outputs by writing a ‘1’ to each corresponding bit in the Direction register of the port.
```
 PORTA.DIR |= PIN0_bm | PIN3_bm;  
```

Tip: The full code example is also available in the Appendix section.