Table 1. Available Interrupt Vectors and Sources| Offset |
Name |
Vector Description |
Conditions |
|---|
| 0x00 |
Slave |
TWI Slave
interrupt |
- DIF: Data Interrupt Flag
in SSTATUS set
- APIF: Address or Stop
Interrupt Flag in SSTATUS set
|
| 0x02 |
Master |
TWI Master interrupt |
- RIF: Read Interrupt Flag
in MSTATUS set
- WIF: Write Interrupt Flag
in MSTATUS set
|
When an interrupt condition occurs,
the corresponding Interrupt Flag is set in the Master register (TWI.MSTATUS) or Slave
Status register (TWI.SSTATUS).
When several interrupt request conditions are supported
by an interrupt vector, the interrupt requests are ORed together into one combined interrupt
request to the Interrupt Controller. The user must read the peripheral's INTFLAGS register to
determine which of the interrupt conditions are present.