TWI

Figure 1. TWI - Timing Requirements
Table 1. TWI - Timing Characteristics
Symbol Description Condition   Min. Typ. Max. Unit
fSCL SCL clock frequency §§ 0   1000 kHz
VIH Input high voltage §§ 0.7×VDD     V
VIL Input low voltage §§     0.3×VDD V
VHYS Hysteresis of Schmitt trigger inputs §§ 0.1×VDD   0.4×VDD V
VOL Output low voltage Iload=20mA, Fast mode+     0.2VDD V
Iload=3mA, Normal mode, VDD>2V     0.4V
Iload=3mA, Normal mode, VDD≤2V     0.2×VDD
IOL Low level output current fSCL≤400kHz, VOL=0.4V 3mA     mA
fSCL≤1MHz, VOL=0.4V 20mA    
CB Capacitive load for each bus line fSCL≤100kHz     400 pF
fSCL≤400kHz     400
fSCL≤1MHz     550
tR Rise time for both SDA and SCL fSCL≤100kHz -   1000 ns
fSCL≤400kHz 20   300
fSCL≤1MHz -   120
tOF Output fall time from VIHmin to VILmax 10pF < Capacitance of bus line < 400pF fSCL≤400kHz 20+0.1×CB   300 ns
fSCL≤1MHz 20+0.1×CB   120
tSP Spikes suppressed by Input filter   0   50 ns
IL Input current for each I/O pin 0.1×VDD<VI<0.9×VDD     1 µA
CI Capacitance for each I/O pin       10 pF
RP Value of pull-up resistor fSCL≤100kHz (VDD-VOL(max)) /IOL   1000ns/(0.8473×CB) Ω
fSCL≤400kHz     300ns/(0.8473×CB)
fSCL≤1MHz     120ns/(0.8473×CB)
tHD;STA Hold time (repeated) START condition fSCL≤100kHz 4.0     µs
fSCL≤400kHz 0.6    
fSCL≤1MHz 0.26    
tLOW Low period of SCL Clock fSCL≤100kHz 4.7     µs
fSCL≤400kHz 1.3    
fSCL≤1MHz 0.5    
tHIGH High period of SCL Clock fSCL≤100kHz 4.0     µs
fSCL≤400kHz 0.6    
fSCL≤1MHz 0.26    
tSU;STA Set-up time for a repeated START condition fSCL≤100kHz 4.7     µs
fSCL≤400kHz 0.6    
fSCL≤1MHz 0.26    
tHD;DAT Data hold time fSCL≤100kHz 0   3.45 µs
fSCL≤400kHz 0   0.9
fSCL≤1MHz 0   0.45
tSU;DAT Data setup time fSCL≤100kHz 250     ns
fSCL≤400kHz 100    
fSCL≤1MHz 50    
tSU;STO Setup time for STOP condition fSCL≤100kHz 4     µs
fSCL≤400kHz 0.6    
fSCL≤1MHz 0.26    
tBUF Bus free time between a STOP and START condition fSCL≤100kHz§ 4.7     µs
fSCL≤400kHz 1.3    
fSCL≤1MHz 0.5    
Parent topic: Electrical Characteristics ATtiny1614/1616/1617