Multiplexed Signals

Table 1. PORT Function Multiplexing
QFN 24-pin	QFN 20-pin	SOIC 20-pin	SOIC 14-pin	Pin Name ^(1,2)	Other/Special	ADC0	ADC1	PTC⁽³⁾	AC0	AC1	AC2	DAC0	USART0	SPI0	TWI0	TCA0	TCBn	TCD0	CCL
23	19	16	10	PA0	RESET UPDI	AIN0													LUT0-IN0
24	20	17	11	PA1	BREAK	AIN1							`TXD`	MOSI	`SDA`				LUT0-IN1
1	1	18	12	PA2	EVOUT0	AIN2							`RxD`	MISO	`SCL`				LUT0-IN2
2	2	19	13	PA3	EXTCLK	AIN3							`XCK`	SCK		WO3	TCB1 WO
3	3	20	14	GND
4	4	1	1	VDD
5	5	2	2	PA4		AIN4	AIN0	X0/Y0					`XDIR`	SS		WO4		WOA	LUT0-OUT
6	6	3	3	PA5	VREFA	AIN5	AIN1	X1/Y1	OUT	AINN0						WO5	TCB0 WO	WOB
7	7	4	4	PA6		AIN6	AIN2	X2/Y2	AINN0	AINP1	AINP0	OUT
8	8	5	5	PA7		AIN7	AIN3	X3/Y3	AINP0	AINP0	AINN0								LUT1-OUT
9				PB7			AIN4			AINN1	AINP3
10				PB6			AIN5		AINP3		AINN1
11	9	6		PB5	CLKOUT	AIN8		X12/Y12	AINP1		AINP2					`WO2`
12	10	7		PB4		AIN9		X13/Y13	AINN1	AINP3						`WO1`			`LUT0-OUT`
13	11	8	6	PB3	TOSC1					OUT			RxD			`WO0`
14	12	9	7	PB2	TOSC2, EVOUT1						OUT		TxD			WO2
15	13	10	8	PB1		AIN10		X4/Y4	AINP2				XCK		SDA	WO1
16	14	11	9	PB0		AIN11		X5/Y5		AINP2	AINP1		XDIR		SCL	WO0
17	15	12		PC0			AIN6	X6/Y6						`SCK`			`TCB0 WO`	WOC
18	16	13		PC1			AIN7	X7/Y7						`MISO`				WOD	`LUT1-OUT`
19	17	14		PC2	EVOUT2		AIN8	X9/Y8						`MOSI`
20	18	15		PC3			AIN9	X9/Y9						`SS`		`WO3`			LUT1-IN0
21				PC4	`BREAK`		AIN10	X10/Y10								`WO4`	`TCB1 WO`		LUT1-IN1
22				PC5			AIN11	X11/Y11								`WO5`			LUT1-IN2

Note:

Pins names are of type Pxn, with x being the PORT instance (A,B) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event input.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Every PTC line can be configured as X-line or Y-line.

Tip: Signals on alternative pin locations are in typewriter font.