Slave Mode Transmission (10-Bit Addressing)

The following section describes the sequence of events when using the I2C in Slave mode transmission.

  1. 1.Master device issues a Start condition. Once the Start is detected, the slave hardware sets the Start Condition Interrupt Flag (SCIF).
  2. 2.Master transmits the 10-bit high address byte with R/W cleared.
  3. 3.The received address is compared to the values in the I2CxADR registers.

    If the slave is configured in 10-bit Addressing mode (no masking), the received high address byte is compared to the values in the I2CxADR1 and I2CxADR3 registers. In 10-bit Addressing mode with masking, the received address is masked with the value of I2CxADR3, and then compared to the value of I2CxADR1. If a match occurs, the R/W bit information (bit ‘0’ of the matching address) is transferred to the Read Information (R) bit of the I2CxSTAT0 register, the Data (D) bit of the I2CxSTAT0 register is cleared, and the Address Interrupt Flag (ADRIF) bit is set. If ABD is cleared, the matching address is copied into the I2CxADB1 register. If ABD is set, the matching address is copied into the receive buffer, I2CxRXB, setting the Receive Buffer Full (RXBF) and I2C Receive Interrupt Flag (I2CxRXIF) bits. I2CxRXIF is a read-only bit, and must be cleared by setting the Clear Buffer (CLRBF) bit or reading I2CxRXB. If there is not an address match, the module goes idle.

  4. 4.When ADRIF is set, if the Address Interrupt and Hold Enable (ADRIE) bit is set and the Clock Stretching Disable (CSD) bit is cleared, the slave hardware sets the Slave Clock Stretching (CSTR) bit and the generic I2CxIF Flag bit. This allows time for the slave to read either I2CxADB1 or I2CxRXB and selectively ACK/NACK based on the received address. When the slave has finished processing the address, the software clears CSTR and ADRIF, which releases the clock and clears the I2CxIF bit.
  5. 5.Master transmits the 9th clock pulse, and the slave hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow, the slave hardware automatically generates a NACK sequence and the module goes idle.
  6. 6.The master transmits the lower address byte.

    If the slave is configured in 10-bit Addressing mode (no masking), the received low address byte is compared to the values in the I2CxADR0 and I2CxADR2 registers. In 10-bit Addressing mode with masking, the received address is masked with the value of I2CxADR2, and then compared to the value of I2CxADR0. If a match occurs, the Slave Mode Active (SMA) bit is set, the R/W bit information is transferred to the R bit of the I2CxSTAT0 register, the D bit of the I2CxSTAT0 register is cleared, and the ADRIF bit is set. If ABD is cleared, the matching address is copied into the I2CxADB0 register. If ABD is set, the matching address is copied into the receive buffer, I2CxRXB, setting the RXBF and I2CxRXIF bits. I2CxRXIF is a read-only bit, and must be cleared by setting the CLRBF bit or reading I2CxRXB.

  7. 7.When ADRIF is set, if the ADRIE bit is set and the CSD bit is cleared, the slave hardware sets the CSTR bit and the generic I2CxIF bit. This allows time for the slave to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the slave has finished processing the address, the software clears CSTR and ADRIF, which releases the clock and clears the I2CxIF bit.
  8. 8.The master transmits the 9th clock pulse, and the slave hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow, the slave hardware automatically generates a NACK condition and the module goes idle.
  9. 9.After the 9th falling edge of the clock, the Acknowledge Status Time Interrupt and Hold (ACKTIF) bit is set. If the Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is set, the slave hardware sets the CSTR and I2CxIF bits. When the slave is ready, the software clears the CSTR and ACKTIF bits, which releases SCL and clears I2CxIF.
  10. 10.The master issues a Restart condition, and once the slave detects the Restart, the hardware sets the Restart Condition Interrupt Flag (RSCIF), and if the Restart Condition Interrupt Enable (RSCIE) bit is set, I2CxIF is also set.
  11. 11.The master then transmits the high address byte again, but with the R/W bit set. If SMA = 1 and the high address matches, the R/W bit is copied into the R bit of I2CxSTAT0, and the D bit of I2CxSTAT0 is cleared. If ABD is cleared, the matching address is stored in I2CxADB1. If ABD is set, the matching address is copied into I2CxRXB, setting the RXBF and I2CxRXIF bits. I2CxRXIF is a read-only bit, and must be cleared by setting the CLRBF bit or reading I2CxRXB.
  12. 12.When ADRIF is set, if the ADRIE bit is set and the CSD bit is cleared, the slave hardware sets the CSTR bit and the generic I2CxIF bit. This allows time for the slave to read either I2CxADB1 or I2CxRXB and selectively ACK/NACK based on the received address. When the slave has finished processing the address, the software clears CSTR and ADRIF, which releases the clock and clears the I2CxIF bit.
  13. 13.If TXBE = 1, I2CxCNT has a non-zero value, and I2CxTXIF = 1, the slave hardware sets CSTR, and waits for software to load I2CxTXB. I2CxTXB must be loaded to clear I2CxTXIF and release SCL. I2CxCNT is decremented after the byte is transferred to the Shift register.
  14. 14.Master transmits the 9th clock pulse, and the slave hardware copies the value of ACKDT onto SDA.
  15. 15.If the slave issued a NACK, the slave hardware sets the NACK Detect Interrupt Flag (NACKIF) and goes idle. If the slave issued an ACK and the I2CxCNT is non-zero, the master transmits eight clock pulses, and the slave begins to shift out the data byte Most Significant Bit (MSb) first. If I2CxCNT = 0, CNTIF is set.
  16. 16.Master receives data byte from slave, then transmits an ACK/NACK sequence. The slave hardware copies the ACK value into the Acknowledge Status (ACKSTAT) bit, and sets ACKTIF. If the ACKTIE bit is set, the slave hardware sets the CSTR and I2CxIF bits. When the slave is ready, the software clears the CSTR and ACKTIF bits, which releases SCL and clears I2CxIF.
  17. 17.Steps 13-16 continue until the master has received all the requested data. Once all data is received, the master transmits a NACK condition followed by either a Stop condition or Restart condition. The slave hardware sets NACKIF and PCIF, and clears SMA.
Parent topic: Slave Mode Transmission