To begin any I2C communication, the master hardware checks to ensure that the bus is in an Idle state, which means both the SCL and SDA lines are floating high. The master hardware monitors the Bus Free (BFRE) bit to be set, indicating the bus is idle. The master then transmits a Start condition, followed by the address of the slave it intends to communicate with. The slave address can be either 7-bit or 10-bit, depending on the application design.
In 7-bit Addressing mode, the Least Significant bit (LSb) acts as the Read/Write (R/W) bit, while in 10-bit Addressing mode, the LSb of the address high byte is considered the R/W bit. When the R/W bit is set, the master intends to read from the slave. If the R/W bit is cleared, the master intends to write to the slave. If the addressed slave device exists on the bus, it must respond with an Acknowledge (ACK) sequence.
The master then continues to either receive data from the slave, write data to the slave, or a combination of both. Data is always transmitted starting with the Most Significant bit (MSb) first. When the master intends to halt further transmission, it transmits a Stop condition, signaling to the slave that communication is to be terminated, or a Restart condition, signaling the bus that the current master wishes to hold the bus to communicate with the same or other slaves.
Slave mode is selected by configuring the MODE[2:0] bits of the I2CxCON0 register. There are four Slave mode configurations and two Multi-Master modes:
The master device generates the SCL pulses, as well as the Start, Restart, and Stop conditions. Transmission always begins with a Start condition, and can end with either a Stop condition or a Restart condition. When the master has completed all transactions, and is ready to release the bus, it will generate a Stop condition. If the master wishes to stop communicating with one slave, but wants to hold the bus to address another slave, it issues a Restart condition. Control of the bus can only be asserted when the Bus Free (BFRE) bit of the I2CxSTAT0 register is set.
The slave waits until hardware detects a Start condition on the bus. Once a Start condition is detected, the slave waits for the incoming address information to be loaded into the receive Shift register. The address is then compared to the addresses loaded into the I2CxADR registers. If an address match is detected, the slave hardware transfers the address into either the I2CxADB0/1 register or the I2CxRXB register, depending on the state of the ABD bit. If there are no address matches, there is no response from the slave.
When the ABD bit is cleared, the Address Buffer registers, I2CxADB0 and I2CxADB1, are active and used to hold the incoming matching address.
In 7-bit Addressing mode, the incoming address is compared to the addresses stored in the I2CxADR registers. If an address matches, the matching address is loaded into the I2CxADB0 register. In 7-bit Address mode, I2CxADB1 is unused. In 10-bit Addressing mode, the first incoming address byte is the high byte of the 10-bit address, and is compared to the values in the I2CxADR1 and I2CxADR3 registers, and the matching upper address byte is loaded into I2CxADB1. If no match is detected, the module becomes idle. The second incoming byte is the lower byte of the 10-bit address, and is compared to the values in I2CxADR0 and I2CxADR2 registers, and the matching lower address byte is loaded into I2CxADB0.
When the ABD bit is set, the address buffers are inactive. In this case, the matching address is loaded into I2CxRXB. The slave software must read I2CxRXB to continue communication.
Once an address match occurs, the slave either continues to receive data from or transmits data to the master device.