Slave Mode Reception (7-Bit Addressing)

The following section describes the sequence of events when using the I2C in Slave mode reception.

  1. 1.Master device issues a Start condition. Once the Start is detected, the slave hardware sets the Start Condition Interrupt Flag (SCIF).
  2. 2.Master transmits the 7-bit slave address with R/W cleared.
  3. 3.The received address is compared to the values in the I2CxADR registers.

    If the slave is configured in 7-bit Addressing mode (no masking), the received address is independently compared to each of the I2CxADR0/1/2/3 registers. In 7-bit Addressing mode with masking, the received address is masked with the value of I2CxADR1 and I2CxADR3, and then compared to the value of I2CxADR0 and I2CxADR2.

    If a match occurs, the Slave Mode Active (SMA) bit is set, the R/W bit information (bit ‘0’ of the matching address) is transferred to the Read Information (R) bit of the I2CxSTAT0 register, the Data (D) bit of the I2CxSTAT0 register is cleared, and the Address Interrupt Flag (ADRIF) bit is set. If the ABD is cleared, the matching address is copied into the I2CxADB0 register. If ABD is set, the matching address is copied into the receive buffer, I2CxRXB, setting the Receive Buffer Full (RXBF) and I2C Receive Interrupt Flag (I2CxRXIF) bits. I2CRXIF is a read-only bit, and must be cleared by setting the Clear Buffer (CLRBF) bit or reading I2CxRXB.

    If no address match occurs, the module stays idle.

  4. 4.When ADRIF is set, if the Address Interrupt and Hold Enable (ADRIE) bit is set and the Clock Stretching Disable (CSD) bit is cleared, slave hardware sets the Slave Clock Stretching (CSTR) bit and the generic I2CxIF Flag bit. This allows time for the slave to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the slave has finished processing the address, the software clears CSTR and ADRIF, which releases the clock and clears the I2CxIF bit.
  5. 5.Master transmits the 9th clock pulse, and the slave hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow, the slave hardware automatically generates a NACK condition, NACKIF is set, and the module goes idle. The slave hardware checks I2CxCNT. If I2CCNT = 0, the Byte Count Interrupt Flag (CNTIF) is set.
  6. 6.Upon the falling edge of the 9th clock pulse, the Acknowledge Time Interrupt Flag (ACKTIF) bit is set, and if CSD = 0, the slave hardware sets CSTR. This allows time for the slave to read the address from either I2CxADB0 or I2CxRXB. Once complete, the slave software clears CSTR to release the clock, and clears ACKTIF to continue communication.
  7. 7.If the slave transmits a NACK, the master hardware generates a Stop condition. The Stop Condition Interrupt Flag (PCIF) is set when the Stop condition is detected, and the slave goes idle.

    If the slave issued an ACK, the master transmits the first 7 bits of the 8-bit data byte.

  8. 8.If previous data is still in the I2CxRXB register (RXBF = 1 and I2CRXIF = 1) when the first seven bits of the new byte are received into the Shift register, the CSTR bit is set, and the clock is stretched after the 7th falling edge of SCL. This allows the slave software to read I2CxRXB, which clears the RXBF and I2CxRXIF bits, and prevents a receive buffer overflow. Once the RXBF bit is cleared, the software clears CSTR, which releases SCL.
  9. 9.Master hardware transmits the 8th bit of the current data byte into the slave’s receive Shift register, then the slave hardware transfers the complete byte into I2CxRXB, sets the I2CxRXIF, the Data Write Interrupt and Hold Flag (WRIF), the Data (D), and the RXBF bits. I2CxCNT is decremented by one. If the Data Write Interrupt and Hold is enabled (WRIE = 1), the hardware sets CSTR, allowing time for slave software to read I2CxRXB and decide the state of the ACKDT bit before clearing CSTR.
  10. 10.Master transmits the 9th clock pulse. If there are pending errors, such as a receive overflow, the slave hardware automatically generates a NACK sequence, NACKIF is set, and the module goes idle.

    If I2CxCNT is not ‘0’, the hardware transmits the value of the ACKDT bit as the ACK value to the master. It is up to the user to configure the ACKDT bit appropriately. In most cases, the ACKDT bit should be cleared, so that the master receives an ACK (logic low level on SDA during the 9th SCL pulse).

    If I2CxCNT = 0, the hardware transmits the value of the Acknowledge End of Count (ACKCNT) bit as the ACK value to the slave. It is up to the user to properly define the ACKCNT bit. In most cases, this bit should be set, indicating a NACK condition. When the master hardware detects the NACK on the bus, the master hardware will also generate a Stop condition. If the ACKCNT bit is cleared, an ACK will be issued, and the master hardware will not automatically generate the Stop condition.

  11. 11.Upon the falling edge of the 9th clock pulse, the ACKTIF bit is set, and if ACKTIE is also set, the generic I2CxIF bit is set, and if CSD is cleared, the slave hardware sets CSTR. This allows time for the slave to read the data from I2CxRXB. Once complete, the slave software clears CSTR to release the clock, and clears ACKTIF to continue communication.
  12. 12.Go to step 7 and continue until I2CxCNT = 0, or until the master issues a Stop condition.
Parent topic: Slave Mode Reception