Interrupts

The stand-alone I2C module contains additional interrupt features designed to assist with communication functions. In addition to the MSSP module’s Start/Restart Condition (SCIF), Stop Condition (PCIF), Bus Collision (BCLIF), and transmit, receive, and acknowledge (SSPIF) interrupts, the stand-alone I2C module adds an Address Match (ADRIF), Transmit Buffer Empty (TXBE), Receive Buffer Full (RXBF), Bus Time-Out (BTOIF), Data Byte Count (CNTIF), Acknowledge Status Time (ACKTIF), and Not Acknowledge Detect (NACKIF).

The stand-alone I2C module incorporates a new register, the I2C Interrupt Flag register (I2CxPIR), which handles several I2C related interrupts. Additionally, when any of the Flag bits in I2CxPIR becomes set and the associated Interrupt Enable bits in the I2CxPIE register are set, the generic I2C Interrupt Flag (I2CxIF) is also set. If the matching Interrupt Enable bit is set, an interrupt is generated whenever the Interrupt Flag bit is set. If the appropriate Interrupt Enable bit is cleared, the Interrupt flag will still be set when the Interrupt condition occurs, however, no interrupt will be triggered.

Important: The generic I2CxIF bit is read-only and is only cleared by hardware when all the bits in the I2CxPIR register are cleared.

The I2CxPIR contains the following Interrupt Flag bits:

The CNTIF becomes set (CNTIF = 1) when the I2CxCNT register value reaches ‘0’, indicating that all bytes in the data frame have been transmitted or received. CNTIF is set after the 9th falling edge of SCL when the I2CxCNT = 0.

The ACKTIF becomes set (ACKTIF = 1) after the 9th falling edge of SCL for any byte when the device is addressed as a slave in any I2C Slave mode or I2C Multi-Master mode whenever an ACK is detected.

The WRIF becomes set (WRIF = 1) after the 8th falling edge of SCL when the module receives a data byte. This bit is only active in any I2C Slave mode or I2C Multi-Master mode. Once the data byte is received, the WRIF is set, as is the Receive Buffer Full (RXBF) Status bit, the I2C Receive Interrupt Flag (I2CxRXIF) bit, and if the Data Write Interrupt and Hold Enable (WRIE) bit is set, the generic I2CxIF bit is also set. The WRIF bit is read/write and must be cleared by the user software, while the RXBF, I2CxRXIF, and I2CxIF are read-only, and are cleared by reading the I2CxRXB.

The ADRIF becomes set on the 8th falling edge of SCL after the module has received either a matching 7-bit address byte or the matching upper or lower bytes of a 10-bit address. This bit is only active in Slave mode or Multi-Master mode. Upon receiving a matching address byte, the ADRIF bit is set, and if the Address Interrupt and Hold Enable (ADRIE) bit is set, the generic I2CxIF bit is set.

The PCIF is set whenever a Stop condition is detected on the bus.

The RSCIF is set upon the detection of a Restart condition.

The SCIF is set upon the detection of a Start condition.

In addition to the I2CxPIR register, the stand-alone module incorporates the I2C Error register (I2CxERR). The I2CxERR register contains three Interrupt Flag bits that are used to detect bus errors. These bits are read/write and must be cleared by the user software. The I2CxERR register also includes the Enable bits for these three functions.

The I2CxERR register contains the following Interrupt Flag bits:

The BTOIF is set when a bus time-out event occurs. The bus time-out time frame is controlled by the I2C Bus Time-Out (I2CxBTO) register. If a bus time-out event occurs and the module is configured as a slave and is active (SMA = 1), BTOIF is set, the SMA and CSTR bits are cleared, and the module is reset. When the BTOIF becomes set and the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is also set.

Important: The I2CxEIF bit is read-only, and is cleared by hardware when all Error Interrupt Flag bits in the I2CxERR register are cleared.

The BCLIF is set whenever a bus collision is detected. A bus collision occurs any time the SDA input is sampled low while both the SDA and SCL outputs are high. When a bus collision event occurs, the BCLIF becomes set, and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is set, the generic I2CxEIF bit is also set.

The NACKIF is set when either the master or slave is active (SMA = 1 || MMA = 1) and a NACK is detected on the bus. A NACK response occurs on the 9th SCL pulse when the SDA line is released high. When the module is in Master mode, a NACK can be issued when the master has finished receiving data from the slave, or in the event it did not receive a byte. In Slave mode, the slave issues a NACK when it does not receive a matching address, or did not receive the last data byte. A NACK can also be automatically sent if any of the following bits are set, which will set the NACKIF, and if the NACK Detect Interrupt Enable (NACKIE) bit is set, the generic I2CxEIF is also set: