Address Buffers and Registers

The I²C module has two Address Buffer registers, I2CxADB0 and I2CxADB1, that can be used as receive buffers in Slave mode (see Table 2). This differs from the MSSP module in that the MSSP module only used the SSPBUF to receive or transmit an address (or data). The address buffers are enabled via the Address Buffer Disable (ABD) bit. When ABD is cleared, the address buffers are enabled; when the ABD is set, the address buffers are disabled.

When the ABD bit is cleared and in 7-bit Addressing mode, I2CxADB0 is loaded with the matching received slave address and the R/W bit, and I2CxADB1 is unused. In 10-bit Addressing mode, I2CxADB0 is loaded with the lower eight bits of the matching received address, and I2CxADB1 is loaded with the upper eight bits of the matching address, including the R/W bit.

When the ABD bit is set and in 7-bit Addressing mode, I2CxRXB is loaded with the matching received slave address and R/W bit, and neither I2CxADB0/1 are used. In 10-bit Addressing mode, I2CxRXB is loaded with both the high and low matching address bytes. In this case, user software must read I2CxRXB before the receive Shift register will load I2CxRXB with the matching lower address byte. I2CxADB0/1 are also unused in 10-bit Addressing mode.

Table 1. Address Buffer Direction for Slave Modes
Modes	MODE[2:0]	I2CADB0	I2CADB1
Slave (7-bit)	`000`	RX	Unused
Slave (7-bit)	`001`	RX	Unused
Slave (10-bit)	`010`	RX	RX
Slave (10-bit)	`011`	RX	RX

The I²C module has four additional Slave mode Address registers, I2CxADR0/1/2/3. These registers can hold up to four 7-bit slave addresses or up to two 10-bit slave addresses. The I2CxADR0/1/2/3 registers can also be used to form mask registers (see Table 2).

In 7-bit Addressing mode, all four registers can be used to store individual slave addresses. The first byte received in a transmission (address byte) is independently compared to each of the values in the I2CxADR registers. The LSb of the received address byte (R/W bit) is not used in determining a match. If address masking is desired, I2CxADR1 holds the value that is used to mask the address loaded in I2CxADR0, and I2CxADR3 holds the value used to mask I2CxADR2.

Table 2. Slave Mode Address Registers
Modes	MODE[2:0]	I2CADR0	I2CADR1	I2CADR2	I2CADR3
7-bit	`000`	7-bit address	7-bit address	7-bit address	7-bit address
7-bit w/masking	`001`	7-bit address	7-bit mask for I2CxADR0	7-bit address	7-bit mask for I2CxADR2
10-bit	`010`	Lower address byte	Upper address byte	Lower address byte	Upper address byte
10-bit w/masking	`011`	Lower address byte	Upper address byte	Lower address mask	Upper address mask

In 10-bit Addressing mode, I2CxADR0 and I2CxADR1 are combined to hold the 10-bit slave address, and I2CxADR2 and I2CxADR3 are combined to hold a second 10-bit slave address. I2CxADR0 and I2CxADR2 hold the lower eight bits of the 10-bit addresses, while I2CxADR1 and I2CxADR3 hold the upper two bits of the 10-bit addresses, the R/W bits, and the five digit ‘11110’ code assigned to the five Most Significant bits of the address high bytes. If address masking is desired, I2CxADR0 and I2CxADR1 are combined to form the 10-bit slave address, and I2CxADR2 and I2CxADR3 are combined to form the 10-bit address mask. Address masking may be used to ignore the five-bit address code loaded into the Most Significant bits of the upper address byte.

Important: The ‘11110’ code is specified by the I²C Specification, but is not strictly enforced by Microchip. The user must ensure that the correct bit values are loaded into the 10-bit high address byte. If a master device has included that specific code in the address it intends to transmit, the slave must also include those bits in the slave address.