The I2C communication protocol terminology used throughout this document have been adapted from the Phillips I2C Specification and can be found in the table below.
I2C Bus Terminology and Definitions
| Term | Definition |
| Master | The device that initiates a transfer, generates the clock signal and terminates a transfer |
| Slave | The device addressed by the master |
| Multi-Master | A bus containing more than one master device that can initiate communication |
| Transmitter | The device that shifts data out onto the bus |
| Receiver | The device that shifts data in from the bus |
| Arbitration | Procedure that ensures only one master at a time controls the bus |
| Synchronization | Procedure that synchronizes the clock signal between two or more devices on the bus |
| Idle | The state in which no activity occurs on the bus and both bus lines are at a high logic level |
| Active | The state in which one or more devices are communicating on the bus |
| Matching Address | The address byte received by a slave that matches the value that is stored in the I2CxADR0/1/2/3 registers |
| Addressed Slave | Slave device that has received a matching address and is actively being clocked by a master device |
| Write Request | Master transmits an address with the R/W bit clear indicating that it wishes to transmit data to a slave device |
| Read Request | Master transmits an address with the R/W bit set indicating that it wishes to receive data from a slave device |
| Clock Stretching | The action in which a device holds the SCL line low to stall communication |
| Bus Collision | Occurs when the module samples the SDA line and returns a low state while expecting a high state |
| Bus Time-out | Occurs whenever communication stalls for a period longer than acceptable |