I2CxSTAT0

I2C Status Register 0
Note:
  1. 1.This bit holds the R/W bit information following the last received address match. Addresses transmitted by the master do not affect the master’s R bit, and addresses appearing on the bus without a match do not affect the R bit.
  2. 2.I2CxCLK must have a valid clock source selected for this bit to function.
Name:
I2CxSTAT0
Address:
0x0298
Reset:
Access:
Bit76543210
BFRESMAMMARD
AccessRRRRR
Reset00000

Bit 7 – BFRE: Bus Free Status(2)

Bus Free Status(2)

ValueDescription
1 Indicates an idle bus; both SCL and SDA have been high for the time selected by the BFRET bits
0 Bus is not idle

Bit 6 – SMA: Slave Mode Active Status

Slave Mode Active Status

ValueDescription
1 Slave mode is active

Set after the 8th falling SCL edge of a received matching 7-bit slave address

Set after the 8th falling SCL edge of a matching received 10-bit slave low address

Set after the 8th falling SCL edge of a received matching 10-bit slave high w/read address, only after a previous received matching high and low w/write address
0 Slave mode is not active

Cleared when any Restart/Stop condition is detected on the bus

Cleared by BTOIF and BCLIF conditions

Bit 5 – MMA: Master Mode Active Status

Master Mode Active Status

ValueDescription
1 Master mode is active

Set when master state machine asserts a Start condition
0 Master mode is not active
Cleared when BCLIF is set

Cleared when Stop condition is issued

Cleared for BTOIF condition after the master successfully shifts out a Stop condition

Bit 4 – R: Read Information(1)

Read Information(1)

ValueDescription
1 Indicates that the last matching received address was a Read request
0 Indicates that the last matching received address was a Write request

Bit 3 – D: Data

Data

ValueDescription
1 Indicates that the last byte received or transmitted was data
0 Indicates that the last byte received or transmitted was an address