In both 7-bit and 10-bit Master Receive modes, the state of the ABD bit is ignored. Once the complete 7-bit or 10-bit address has been received by the slave, the slave will transmit a data byte. Once the byte has been received by the master, hardware sets the I2CxRXIF bit, which triggers the DMA to read I2CxRXB. Once the DMA has read I2CxRXB, I2CxRXIF is cleared by hardware and the DMA waits for the next occurrence of I2CxRXIF being set.