I2CxSTAT1

I2CxSTAT1

I2C Status Register 1

Note:

1.This bit, when set, will cause a NACK to be issued.
2.Used as a trigger source for DMA operations.
3.This bit is special function; it can only be set by user software and always reads ‘0’.

Name:: I2CxSTAT1
Address:: 0x0299
Reset:
Access:

Bit7	6	5	4	3	2	1	0
TXWE		TXBE		RXRE	CLRBF		RXBF
AccessR/W/HS		R		R/W/HS	R/S		R
Reset0		1		0	0		0

Bit 7 – TXWE: Transmit Write Error Status(1)

Transmit Write Error Status⁽¹⁾

Value	Description
`1`	A new byte of data was written into I2CxTXB when it was full (must be cleared by software)
`0`	No transmit write error occurred

Bit 5 – TXBE: Transmit Buffer Empty Status(2)

Transmit Buffer Empty Status⁽²⁾

Value	Description
`1`	I2CxTXB is empty (cleared by writing to the I2CxTXB register)
`0`	I2CxTXB is full

Bit 3 – RXRE: Receive Read Error Status(1)

Receive Read Error Status⁽¹⁾

Value	Description
`1`	A byte of data was read from I2CxRXB when it was empty (must be cleared by software)
`0`	No receive overflow occurred

Bit 2 – CLRBF: Clear Buffer(3)

Clear Buffer⁽³⁾

Value	Description
`1`	Setting this bit clears/empties the receive and transmit buffers, causing a Reset of RXBF and TXBE Setting this bit clears the I2CxRXIF and I2CxTXIF interrupt flags

Bit 0 – RXBF: Receive Buffer Full Status(2)

Receive Buffer Full Status⁽²⁾

Value	Description
`1`	I2CxRXB is full (cleared by reading the I2CxRXB register)
`0`	I2CxRXB is empty