The CMODE bit field in the CTRLC register controls the communication modes.
The disadvantage of the Asynchronous mode is that the receiver chip and the transmitter chip need to use the same baud rate and exact timing is required. The asynchronous protocols use a separate line for the clock signal, so the chip that generates the clock dictates the communication speed. This is much more flexible in terms of exact timings and creates two roles in the communication: the master that generates the clock and the slave that receives the clock.
In the Synchronous USART mode, an additional clock pin, XCK, is used. Same as the RX and TX pins, XCK has a default pin, and changing the PORTMUX register will also change XCK. Configuring the XCK direction decides if the device is a master (generates clock) or a slave (receives clock).
To activate the Synchronous mode:
- Configure the XCK pin (PA2) direction
as
output;
PORTA.DIR |= PIN2_bm;
- Write 0x01 to the CMODE bit field in
the USARTn.CTRLC register.Figure 2. USART Communication Mode
USART0.CTRLC = USART_CMODE_SYNCHRONOUS_gc;
