Contents

0. Introduction 1. Features 2. Silicon Errata and Data Sheet Clarification Document 3. tinyAVR 0-Series Overview 3.1 Configuration Summary 3.11 Peripheral Summary 4. Block Diagram 5. Pinout 5.1 20-pin SOIC300 5.2 20-pin QFN3x3 6. I/O Multiplexing and Considerations 6.1 Multiplexed Signals 7. Memories 7.1 Overview 7.2 Memory Map 7.3 In-System Reprogrammable Flash Program Memory 7.4 SRAM Data Memory 7.5 EEPROM Data Memory 7.6 User Row 7.7 Signature Bytes 7. 7. 7.8 I/O Memory 7.8 7.8 7.81 Register Summary - GPIOR 7.82 Register Description - GPIOR 7.821 General Purpose I/O Register n 7.9 Memory Section Access from CPU and UPDI on Locked Device 7. 7. 7.10 Configuration and User Fuses (FUSE) 7.10 7.10 7.101 Signature Row Summary (SIGROW) 7.102 Signature Row Description 7.1021 Device ID n 7.1022 Serial Number Byte n 7.1023 Temperature Sensor Calibration n 7.1024 OSC16 Error at 3V 7.1025 OSC16 Error at 5V 7.1026 OSC20 Error at 3V 7.1027 OSC20 Error at 5V 7.10 7.10 7.103 Fuse Summary - FUSE 7.104 Fuse Description 7.1041 Watchdog Configuration 7.1042 BOD Configuration 7.1043 Oscillator Configuration 7.1044 System Configuration 0 7.1045 System Configuration 1 7.1046 Application Code End 7.1047 Boot End 7.1048 Lockbits 8. Peripherals and Architecture 8.1 Peripheral Module Address Map 8.2 Interrupt Vector Mapping 8. 8. 8.3 System Configuration (SYSCFG) 8.3 8.3 8.31 Register Summary - SYSCFG 8.32 Register Description - SYSCFG 8.321 Device Revision ID Register 9. AVR CPU 9.1 Features 9.2 Overview 9.3 Architecture 9.4 Arithmetic Logic Unit (ALU) 9.41 Hardware Multiplier 9.5 Functional Description 9.51 Program Flow 9.52 Instruction Execution Timing 9.53 Status Register 9.54 Stack and Stack Pointer 9.55 Register File 9.551 The X-, Y-, and Z-Registers 9.56 Accessing 16-Bit Registers 9.57 Configuration Change Protection (CCP) 9.571 Sequence for Write Operation to Configuration Change Protected I/O Registers 9.572 Sequence for Execution of Self-Programming 9. 9. 9.6 Register Summary - CPU 9.7 Register Description 9.71 CCP 9.72 SP 9.73 SREG 10. NVMCTRL - Nonvolatile Memory Controller 10.1 Features 10.2 Overview 10.21 Block Diagram 10.22 System Dependencies 10.221 Clocks 10.222 I/O Lines and Connections 10.223 Interrupts 10.224 Events 10.225 Debug Operation 10. 10. 10.3 Functional Description 10.31 Memory Organization 10.311 Flash 10.312 EEPROM 10.313 User Row 10.32 Memory Access 10.321 Read 10.322 Page Buffer Load 10.323 Programming 10.324 Commands 10.3241 Write Command 10.3242 Erase Command 10.3243 Erase-Write Operation 10.3244 Page Buffer Clear Command 10.3245 Chip Erase Command 10.3246 EEPROM Erase Command 10.3247 Fuse Write Command 10.33 Preventing Flash/EEPROM Corruption 10.34 Interrupts 10.35 Sleep Mode Operation 10.36 Configuration Change Protection 10. 10. 10.4 Register Summary - NVMCTRL 10.5 Register Description 10.51 Control A 10.52 Control B 10.53 Status 10.54 Interrupt Control 10.55 Interrupt Flags 10.56 Data 10.57 Address 11. CLKCTRL - Clock Controller 11.1 Features 11.2 Overview 11.21 Block Diagram - CLKCTRL 11.22 Signal Description 11.3 Functional Description 11.31 Sleep Mode Operation 11.3 11.3 11.32 Main Clock Selection and Prescaler 11.33 Main Clock After Reset 11.3 11.3 11.34 Clock Sources 11.341 Internal Oscillators 11.3411 16/20 MHz Oscillator (OSC20M) 11.34111 OSC20M Stored Frequency Error Compensation 11.3412 32 KHz Oscillator (OSCULP32K) 11.342 External Clock Sources 11.3421 External Clock (EXTCLK) 11.35 Configuration Change Protection 11. 11. 11.4 Register Summary - CLKCTRL 11.5 Register Description 11.51 Main Clock Control A 11.52 Main Clock Control B 11.53 Main Clock Lock 11.54 Main Clock Status 11.55 16/20 MHz Oscillator Control A 11.56 16/20 MHz Oscillator Calibration A 11.57 16/20 MHz Oscillator Calibration B 11.58 32 KHz Oscillator Control A 12. SLPCTRL - Sleep Controller 12.1 Features 12.2 Overview 12.21 Block Diagram 12.22 System Dependencies 12.221 Clocks 12.222 I/O Lines and Connections 12.223 Interrupts 12.224 Events 12.225 Debug Operation 12. 12. 12.3 Functional Description 12.31 Initialization 12.32 Operation 12.321 Sleep Modes 12.322 Wake-Up Time 12.33 Configuration Change Protection 12. 12. 12.4 Register Summary - SLPCTRL 12.5 Register Description 12.51 Control A 13. RSTCTRL - Reset Controller 13.1 Features 13.2 Overview 13.21 Block Diagram 13.22 Signal Description 13. 13. 13.3 Functional Description 13.31 Initialization 13.32 Operation 13.321 Reset Sources 13.3211 Power-On Reset (POR) 13.3212 Brown-Out Detector (BOD) Reset Source 13.3213 Software Reset 13.3214 External Reset 13.3215 Watchdog Reset 13.3216 Universal Program Debug Interface (UPDI) Reset 13.322 Reset Time 13.33 Sleep Mode Operation 13.34 Configuration Change Protection 13. 13. 13.4 Register Summary - RSTCTRL 13.5 Register Description 13.51 Reset Flag Register 13.52 Software Reset Register 14. CPUINT - CPU Interrupt Controller 14.1 Features 14.2 Overview 14.21 Block Diagram 14.22 Signal Description 14.23 System Dependencies 14.231 Clocks 14.232 I/O Lines and Connections 14.233 Interrupts 14.234 Events 14.235 Debug Operation 14. 14. 14.3 Functional Description 14.31 Initialization 14.32 Operation 14.321 Enabling, Disabling, and Resetting 14.322 Interrupt Vector Locations 14.323 Interrupt Response Time 14.324 Interrupt Priority 14.325 Scheduling of Normal Priority Interrupts 14.3251 Non-Maskable Interrupts (NMI) 14.3252 Static Scheduling 14.3253 Round Robin Scheduling 14.3254 Compact Vector Table 14.33 Events 14.34 Sleep Mode Operation 14.35 Configuration Change Protection 14. 14. 14.4 Register Summary - CPUINT 14.5 Register Description 14.51 Control A 14.52 Status 14.53 Interrupt Priority Level 0 14.54 Interrupt Vector with Priority Level 1 15. EVSYS - Event System 15.1 Features 15.2 Overview 15.21 Block Diagram 15.22 Signal Description 15.23 System Dependencies 15.231 Clocks 15.232 I/O Lines 15. 15. 15.3 Functional Description 15.31 Initialization 15.32 Operation 15.321 Event User Multiplexer Setup 15.322 Event System Channel 15.323 Event Generators 15.324 Software Event 15.33 Interrupts 15.34 Sleep Mode Operation 15.35 Debug Operation 15.36 Synchronization 15.37 Configuration Change Protection 15. 15. 15.4 Register Summary - EVSYS 15.5 Register Description 15.51 Asynchronous Channel Strobe 15.52 Synchronous Channel Strobe 15.53 Asynchronous Channel n Generator Selection 15.54 Synchronous Channel n Generator Selection 15.55 Asynchronous User Channel n Input Selection 15.56 Synchronous User Channel n Input Selection 16. PORTMUX - Port Multiplexer 16.1 Overview 16. 16. 16.2 Register Summary - PORTMUX 16.3 Register Description 16.31 Control A 16.32 Control B 16.33 Control C 16.34 Control D 17. PORT - I/O Pin Configuration 17.1 Features 17.2 Overview 17.21 Block Diagram 17.22 Signal Description 17.23 System Dependencies 17.231 Clocks 17.232 I/O Lines and Connections 17.233 Interrupts 17.234 Events 17.235 Debug Operation 17. 17. 17.3 Functional Description 17.31 Initialization 17.32 Operation 17.321 Basic Functions 17.322 Virtual Ports 17.323 Pin Configuration 17.33 Interrupts 17.34 Events 17.35 Sleep Mode Operation 17.36 Synchronization 17.37 Configuration Change Protection 17. 17. 17.4 Register Summary - PORT 17.5 Register Description - Ports 17.51 Data Direction 17.52 Data Direction Set 17.53 Data Direction Clear 17.54 Data Direction Toggle 17.55 Output Value 17.56 Output Value Set 17.57 Output Value Clear 17.58 Output Value Toggle 17.59 Input Value 17.510 Interrupt Flags 17.511 Pin n Control 17. 17. 17.6 Register Summary - VPORT 17.7 Register Description - Virtual Ports 17.71 Data Direction 17.72 Output Value 17.73 Input Value 17.74 Interrupt Flag 18. BOD - Brown-out Detector 18.1 Features 18.2 Overview 18.21 Block Diagram 18.22 System Dependencies 18.221 Clocks 18.222 I/O Lines and Connections 18.223 Interrupts 18.224 Events 18.225 Debug Operation 18. 18. 18.3 Functional Description 18.31 Initialization 18.32 Interrupts 18.33 Sleep Mode Operation 18.34 Synchronization 18.35 Configuration Change Protection 18. 18. 18.4 Register Summary - BOD 18.5 Register Description 18.51 Control A 18.52 Control B 18.53 VLM Control A 18.54 Interrupt Control 18.55 VLM Interrupt Flags 18.56 VLM Status 19. VREF - Voltage Reference 19.1 Features 19.2 Overview 19.21 Block Diagram 19. 19. 19.3 Functional Description 19.31 Initialization 19. 19. 19.4 Register Summary - VREF 19.5 Register Description 19.51 Control A 19.52 Control B 20. WDT - Watchdog Timer 20.1 Features 20.2 Overview 20.21 Block Diagram 20.22 Signal Description 20.23 System Dependencies 20.231 Clocks 20.232 I/O Lines and Connections 20.233 Interrupts 20.234 Events 20.235 Debug Operation 20. 20. 20.3 Functional Description 20.31 Initialization 20.32 Operation 20.321 Normal Mode 20.322 Window Mode 20.323 Configuration Protection and Lock 20.33 Events 20.34 Interrupts 20.35 Sleep Mode Operation 20.36 Synchronization 20.37 Configuration Change Protection 20. 20. 20.4 Register Summary - WDT 20.5 Register Description 20.51 Control A 20.52 Status 21. TC0/1 – 16-bit Timer/Counter Type 0 and 1 21.1 Features 21.2 Overview 21.21 Block Diagram 21.22 Signal Description 21.23 System Dependencies 21.231 Clocks 21.232 I/O Lines and Connections 21.233 Interrupts 21.234 Events 21.235 Debug Operation 21. 21. 21.3 Functional Description 21.31 Definitions 21.32 Initialization 21.33 Operation 21.331 Normal Operation 21.332 Double Buffering 21.333 Changing the Period 21.334 Compare Channel 21.3341 Waveform Generation 21.3342 Frequency (FRQ) Waveform Generation 21.3343 Single-slope PWM Generation 21.3344 Dual-slope PWM 21.3345 Port Override for Waveform Generation 21.335 Timer/Counter Commands 21.336 Split Mode - Two 8-Bit Timer/Counters 21.34 Events 21.35 Interrupts 21.36 Sleep Mode Operation 21.37 Configuration Change Protection 21. 21. 21.4 Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0) 21.5 Register Description - Normal Mode 21.51 Control A 21.52 Control B - Normal Mode 21.53 Control C - Normal Mode 21.54 Control D 21.55 Control Register E Clear - Normal Mode 21.56 Control Register E Set - Normal Mode 21.57 Control Register F Clear 21.58 Control Register F Set 21.59 Event Control 21.510 Interrupt Control Register - Normal Mode 21.511 Interrupt Flag Register - Normal Mode 21.512 Debug Control Register 21.513 Temporary Bits for 16-Bit Access 21.514 Counter Register - Normal Mode 21.515 Period Register - Normal Mode 21.516 Compare n Register - Normal Mode 21.517 Period Buffer Register 21.518 Compare n Buffer Register 21. 21. 21.6 Register Summary - TCA in Split Mode (CTRLD.SPLITM=1) 21.7 Register Description - Split Mode 21.71 Control A 21.72 Control B - Split Mode 21.73 Control C - Split Mode 21.74 Control D 21.75 Control Register E Clear - Split Mode 21.76 Control Register E Set - Split Mode 21.77 Interrupt Control Register - Split Mode 21.78 Interrupt Flag Register - Split Mode 21.79 Debug Control Register 21.710 Low Byte Timer Counter Register - Split Mode 21.711 High Byte Timer Counter Register - Split Mode 21.712 Low Byte Timer Period Register - Split Mode 21.713 High Byte Period Register - Split Mode 21.714 Compare Register n For Low Byte Timer - Split Mode 21.715 High Byte Compare Register n - Split Mode 22. TCB - 16-bit Timer/Counter Type B 22.1 Features 22.2 Overview 22.21 Block Diagram 22.211 Noise Canceler 22.22 Signal Description 22.23 System Dependencies 22.231 Clocks 22.232 I/O Lines and Connections 22.233 Interrupts 22.234 Events 22.235 Debug Operation 22. 22. 22.3 Functional Description 22.31 Definitions 22.32 Initialization 22.33 Operation 22.331 Modes 22.3311 Periodic Interrupt Mode 22.3312 Time-Out Check Mode 22.3313 Input Capture on Event Mode 22.3314 Input Capture Frequency Measurement Mode 22.3315 Input Capture Pulse-Width Measurement Mode 22.3316 Input Capture Frequency and Pulse-Width Measurement Mode 22.3317 Single-Shot Mode 22.3318 8-Bit PWM Mode 22.332 Output 22.333 Noise Canceler 22.334 Synchronized with TCAn 22.34 Events 22.35 Interrupts 22.36 Sleep Mode Operation 22.37 Synchronization 22.38 Configuration Change Protection 22. 22. 22.4 Register Summary - TCB 22.5 Register Description 22.51 Control A 22.52 Control B 22.53 Event Control 22.54 Interrupt Control 22.55 Interrupt Flags 22.56 Status 22.57 Debug Control 22.58 Temporary Value 22.59 Count 22.510 Capture/Compare 23. RTC - Real-Time Counter 23.1 Features 23.2 Overview 23.21 Block Diagram 23.22 Signal Description 23.23 System Dependencies 23.231 Clocks 23.232 I/O Lines and Connections 23.233 Interrupts 23.234 Events 23.235 Debug Operation 23. 23. 23.3 RTC Functional Description 23.31 Initialization 23.311 Configure the Clock CLK_RTC 23.312 Configure RTC 23.32 Operation - RTC 23.321 Enabling, Disabling, and Resetting 23.4 PIT Functional Description 23.41 Initialization 23.42 Operation - PIT 23.421 Enabling, Disabling, and Resetting 23.422 PIT Interrupt Timing 23.5 Events 23.6 Interrupts 23.7 Sleep Mode Operation 23.8 Synchronization 23.9 Configuration Change Protection 23. 23. 23.10 Register Summary - RTC 23.11 Register Description 23.111 Control A 23.112 Status 23.113 Interrupt Control 23.114 Interrupt Flag 23.115 Temporary 23.116 Debug Control 23.117 Clock Selection 23.118 Count 23.119 Period 23.1110 Compare 23.1111 Periodic Interrupt Timer Control A 23.1112 Periodic Interrupt Timer Status 23.1113 PIT Interrupt Control 23.1114 PIT Interrupt Flag 23.1115 Periodic Interrupt Timer Debug Control 24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 24.1 Features 24.2 Overview 24.21 Signal Description 24.22 System Dependencies 24.221 Clocks 24.222 I/O Lines and Connections 24.223 Interrupts 24.224 Events 24.225 Debug Operation 24.226 Block Diagram 24. 24. 24.3 Functional Description 24.31 Initialization 24.32 Operation 24.321 Clock Generation 24.3211 Internal Clock Generation - The Fractional Baud Rate Generator 24.3212 External Clock 24.3213 Double Speed Operation 24.3214 Synchronous Clock Operation 24.3215 Master SPI Mode Clock Generation 24.322 Frame Formats 24.3221 Parity 24.3222 SPI Frame Formats 24.323 Data Transmission - USART Transmitter 24.3231 Sending Frames 24.3232 Disabling the Transmitter 24.324 Data Reception - USART Receiver 24.3241 Receiving Frames 24.3242 Receiver Error Flags 24.3243 Parity Checker 24.3244 Disabling the Receiver 24.3245 Flushing the Receive Buffer 24.3246 Asynchronous Data Reception 24.32461 Asynchronous Clock Recovery 24.32462 Asynchronous Data Recovery 24.3247 Asynchronous Operational Range 24.325 USART in Master SPI mode 24.3251 USART SPI vs. SPI 24.326 RS-485 Mode of Operation 24.327 Start Frame Detection 24.328 Break Character Detection and Auto-Baud 24.329 One-Wire Mode 24.3210 Multiprocessor Communication Mode 24.32101 Using Multiprocessor Communication Mode 24.3211 IRCOM Mode of Operation 24.32111 Overview 24.32112 Block Diagram 24.32113 IRCOM and Event System 24.33 Events 24.34 Interrupts 24.35 Configuration Change Protection 24. 24. 24.4 Register Summary - USART 24.5 Register Description 24.51 Receiver Data Register Low Byte 24.52 Receiver Data Register High Byte 24.53 Transmit Data Register Low Byte 24.54 Transmit Data Register High Byte 24.55 USART Status Register 24.56 Control A 24.57 Control B 24.58 Control C - Async Mode 24.59 Control C - Master SPI Mode 24.510 Baud Register 24.511 Debug Control Register 24.512 IrDA Control Register 24.513 IRCOM Transmitter Pulse Length Control Register 24.514 IRCOM Receiver Pulse Length Control Register 25. SPI - Serial Peripheral Interface 25.1 Features 25.2 Overview 25.21 Block Diagram 25.22 Signal Description 25.23 System Dependencies 25.231 Clocks 25.232 I/O Lines and Connections 25.233 Interrupts 25.234 Events 25.235 Debug Operation 25. 25. 25.3 Functional Description 25.31 Initialization 25.32 Operation 25.321 Master Mode Operation 25.3211 SS Pin Functionality in Master Mode - Multi-Master Support 25.3212 Normal Mode 25.3213 Buffer Mode 25.322 Slave Mode 25.3221 SS Pin Functionality in Slave Mode 25.3222 Normal Mode 25.3223 Buffer Mode 25.323 Data Modes 25.33 Interrupts 25.34 Sleep Mode Operation 25.35 Configuration Change Protection 25. 25. 25.4 Register Summary - SPI 25.5 Register Description 25.51 Control A 25.52 Control B 25.53 Interrupt Control 25.54 Interrupt Flags 25.55 Data 26. TWI - Two-Wire Interface 26.1 Features 26.2 Overview 26.21 Block Diagram 26.22 Signal Description 26.23 System Dependencies 26.231 Clocks 26.232 I/O Lines and Connections 26.233 Interrupts 26.234 Events 26.235 Debug Operation 26. 26. 26.3 Functional Description 26.31 Initialization 26.32 General TWI Bus Concepts 26.321 Start and Stop Conditions 26.322 Bit Transfer 26.323 Address Packet 26.324 Data Packet 26.325 Transaction 26.326 Clock and Clock Stretching 26.327 Arbitration 26.328 Synchronization 26.33 TWI Bus State Logic 26.34 Operation 26.341 Electrical Characteristics 26.342 TWI Master Operation 26.3421 Clock Generation 26.3422 Transmitting Address Packets 26.34221 Case M1: Arbitration Lost or Bus Error during Address Packet 26.34222 Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave 26.34223 Case M3: Address Packet Transmit Complete - Direction Bit Cleared 26.34224 Case M4: Address Packet Transmit Complete - Direction Bit Set 26.3423 Transmitting Data Packets 26.3424 Receiving Data Packets 26.3425 Quick Command Mode 26.343 TWI Slave Operation 26.3431 Receiving Address Packets 26.34311 Case S1: Address Packet Accepted - Direction Bit Set 26.34312 Case S2: Address Packet Accepted - Direction Bit Cleared 26.34313 Case S3: Collision 26.34314 Case S4: STOP Condition Received 26.3432 Receiving Data Packets 26.3433 Transmitting Data Packets 26.344 Smart Mode 26.35 Events 26.36 Interrupts 26.37 Sleep Mode Operation 26.38 Synchronization 26.39 Configuration Change Protection 26. 26. 26.4 Register Summary - TWI 26.5 Register Description 26.51 Control A 26.52 Debug Control 26.53 Master Control A 26.54 Master Control B 26.55 Master Status 26.56 Master Baud Rate 26.57 Master Address 26.58 Master DATA 26.59 Slave Control A 26.510 Slave Control B 26.511 Slave Status 26.512 Slave Address 26.513 Slave Data 26.514 Slave Address Mask 27. CRCSCAN - Cyclic Redundancy Check Memory Scan 27.1 Features 27.2 Overview 27.21 Block Diagram 27.22 System Dependencies 27.221 Clocks 27.222 I/O Lines and Connections 27.223 Interrupts 27.224 Events 27.225 Debug Operation 27. 27. 27.3 Functional Description 27.31 Initialization 27.32 Operation 27.321 Checksum 27.33 Interrupts 27.34 Sleep Mode Operation 27.35 Configuration Change Protection 27. 27. 27.4 Register Summary - CRCSCAN 27.5 Register Description 27.51 Control A 27.52 Control B 27.53 Status 28. CCL - Configurable Custom Logic 28.1 Features 28.2 Overview 28.21 Signal Description 28.22 System Dependencies 28.221 I/O Lines 28.222 Debug Operation 28.3 Functional Description 28.31 Initialization 28.32 Operation 28.321 Enabling, Disabling, and Resetting 28.322 Look-Up Table Logic 28.323 Truth Table Inputs Selection 28.324 Filter 28.325 Edge Detector 28.326 Sequential Logic 28.33 Events 28.34 Sleep Mode Operation 28.35 Configuration Change Protection 28. 28. 28.4 Register Summary - CCL 28.5 Register Description 28.51 Control A 28.52 Sequential Control 0 28.53 LUT n Control A 28.54 LUT n Control B 28.55 LUT n Control C 28.56 TRUTHn 29. AC – Analog Comparator 29.1 Features 29.2 Overview 29.21 Block Diagram 29.22 Signal Description 29.23 System Dependencies 29.231 Clocks 29.232 I/O Lines and Connections 29.233 Interrupts 29.234 Events 29.235 Debug Operation 29. 29. 29.3 Functional Description 29.31 Initialization 29.32 Operation 29.321 Input Hysteresis 29.322 Input Sources 29.3221 Pin Inputs 29.3222 Internal Inputs 29.323 Low-Power Mode 29.33 Events 29.34 Interrupts 29.35 Sleep Mode Operation 29.36 Configuration Change Protection 29. 29. 29.4 Register Summary - AC 29.5 Register Description 29.51 Control A 29.52 MUX Control A 29.53 Interrupt Control 29.54 Status 30. ADC - Analog-to-Digital Converter 30.1 Features 30.2 Overview 30.21 Block Diagram 30.22 Signal Description 30.23 System Dependencies 30.231 Clocks 30.232 I/O Lines and Connections 30.233 Interrupts 30.234 Events 30.235 Debug Operation 30.24 Definitions 30. 30. 30.3 Functional Description 30.31 Initialization 30.32 Operation 30.321 Starting a Conversion 30.322 Clock Generation 30.323 Conversion Timing 30.324 Changing Channel or Reference Selection 30.3241 ADC Input Channels 30.3242 ADC Voltage Reference 30.3243 Analog Input Circuitry 30.325 ADC Conversion Result 30.326 Temperature Measurement 30.327 Window Comparator Mode 30.33 Events 30.34 Interrupts 30.35 Sleep Mode Operation 30.36 Synchronization 30.37 Configuration Change Protection 30. 30. 30.4 Register Summary - ADCn 30.5 Register Description 30.51 Control A 30.52 Control B 30.53 Control C 30.54 Control D 30.55 Control E 30.56 Sample Control 30.57 MUXPOS 30.58 Command 30.59 Event Control 30.510 Interrupt Control 30.511 Interrupt Flags 30.512 Debug Run 30.513 Temporary 30.514 Result 30.515 Window Comparator Low Threshold 30.516 Window Comparator High Threshold 30.517 Calibration 31. UPDI - Unified Program and Debug Interface 31.1 Features 31.2 Overview 31.21 Block Diagram 31.22 System Dependencies 31.221 Clocks 31.222 I/O Lines and Connections 31.223 Events 31.224 Power Management 31. 31. 31.3 Functional Description 31.31 Principle of Operation 31.311 UPDI UART 31.312 BREAK Character 31.32 Operation 31.321 UPDI Enable with Fuse Override of RESET Pin 31.322 UPDI Enable with 12V Override of RESET Pin 31.323 UPDI Disable 31.324 Output Enable Timer Protection for GPIO Configuration 31.325 UPDI Communication Error Handling 31.326 Direction Change 31.33 UPDI Instruction Set 31.331 LDS - Load Data from Data Space Using Direct Addressing 31.332 STS - Store Data to Data Space Using Direct Addressing 31.333 LD - Load Data from Data Space Using Indirect Addressing 31.334 ST - Store Data from Data Space Using Indirect Addressing 31.335 LCDS - Load Data from Control and Status Register Space 31.336 STCS (Store Data to Control and Status Register Space) 31.337 REPEAT - Set Instruction Repeat Counter 31.338 KEY - Set Activation KEY 31.34 System Clock Measurement with UPDI 31.35 Interbyte Delay 31.36 System Information Block 31.37 Enabling of KEY Protected Interfaces 31.371 Chip Erase 31.372 NVM Programming 31.373 User Row Programming 31.38 Events 31.39 Sleep Mode Operation 31. 31. 31.4 Register Summary - UPDI 31.5 Register Description 31.51 Status A 31.52 Status B 31.53 Control A 31.54 Control B 31.55 ASI Key Status 31.56 ASI Reset Request 31.57 ASI Control A 31.58 ASI System Control A 31.59 ASI System Status 31.510 ASI CRC Status 32. Electrical Characteristics 32.1 Disclaimer 32.2 Absolute Maximum Ratings 32.3 General Operating Ratings 32.4 Power Consumption 32.5 Wake-Up Time 32.6 Power Consumption of Peripherals 32.7 BOD and POR Characteristics 32.8 External Reset Characteristics 32.9 Oscillators and Clocks 32.10 I/O Pin Characteristics 32.11 USART 32.12 SPI 32.13 TWI 32.14 VREF 32.15 ADC 32.16 AC 32.17 UPDI Timing 32.18 Programming Time 33. Typical Characteristics 33.1 Power Consumption 33.11 Supply Currents in Active Mode 33.12 Supply Currents in Idle Mode 33.13 Supply Currents in Standby Mode 33.14 Supply Currents in Power-Down Mode 33.2 GPIO 33.3 VREF Characteristics 33.4 BOD Characteristics 33.5 ADC Characteristics 33.6 AC Characteristics 33.7 OSC20M Characteristics 33.8 OSCULP32K Characteristics 34. Errata 34. 34. 34.1 Errata - ATtiny806/1606 35. Ordering Information 35.1 Product Information 35.2 Product Identification System 36. Package Drawings 36.1 Online Package Drawings 36.2 20-Pin SOIC300 36.3 20-Pin VQFN 37. Thermal Considerations 37.1 Thermal Resistance Data 37.2 Junction Temperature 38. Instruction Set Summary 39. Conventions 39.1 Numerical Notation 39.2 Memory Size and Type 39.3 Frequency and Time 39.4 Registers and Bits 40. Acronyms and Abbreviations 41. Data Sheet Revision History 41.1 Rev. B - 07/2019 41.2 Revision History The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service