The
ATmega48/V provides two Lock bits and the other
devices provides six Lock bits. These
can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features
listed in Table. Lock Bit Protection Modes in this section. The Lock bits can only be
erased to “1” with the Chip Erase command.
The
ATmega48/V has no separate Boot Loader section, and the
Store Program Memory (SPM) instruction is enabled for the whole Flash if the SELFPRGEN fuse
is programmed (“0”). Otherwise the SPM instruction is disabled.
Table 1. Lock Bit Byte(1)| Lock Bit Byte |
Bit No. |
Description |
Default Value |
|---|
| |
7 |
– |
1
(unprogrammed) |
| |
6 |
– |
1
(unprogrammed) |
| BLB12(2) |
5 |
Boot Lock
bit |
1 (unprogrammed) |
| BLB11(2) |
4 |
Boot Lock bit |
1 (unprogrammed) |
| BLB02(2) |
3 |
Boot Lock bit |
1 (unprogrammed) |
| BLB01(2) |
2 |
Boot Lock bit |
1 (unprogrammed) |
| LB2 |
1 |
Lock bit |
1 (unprogrammed) |
| LB1 |
0 |
Lock bit |
1 (unprogrammed) |
Note:
- '1' means unprogrammed, '0' means
programmed.
- Only on ATmega88/V and ATmega168/V.
Table 2. Lock Bit Protection Modes(1)(2)| Memory Lock Bits |
Protection Type |
|---|
| LB Mode |
LB2 |
LB1 |
|---|
| 1 |
1 |
1 |
No memory lock features enabled. |
| 2 |
1 |
0 |
Further
programming of the Flash and EEPROM is disabled in Parallel and Serial
Programming mode. The Fuse bits are locked in both Serial and Parallel
Programming mode.(1) |
| 3 |
0 |
0 |
Further
programming and verification of the Flash and EEPROM is disabled in Parallel
and Serial Programming mode. The Boot Lock bits and Fuse bits are locked in
both Serial and Parallel Programming mode.(1) |
Note:
- Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
- '1' means unprogrammed, '0' means
programmed.
Table 3. Lock Bit Protection - BLB0
Mode(1)(2). (Only ATmega88/V and ATmega168/V.)| BLB0 Mode |
BLB02 |
BLB01 |
|
|---|
| 1 |
1 |
1 |
No
restrictions for SPM or Load Program Memory (LPM) instruction accessing the
Application section. |
| 2 |
1 |
0 |
SPM is not allowed to write to the Application section. |
| 3 |
0 |
0 |
SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. |
| 4 |
0 |
1 |
LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. |
Table 4. Lock Bit Protection - BLB1
Mode(1)(2)
(Only ATmega88/V and ATmega168/V.)| BLB1 Mode |
BLB12 |
BLB11 |
|
|---|
| 1 |
1 |
1 |
No restrictions for SPM or LPM
accessing the Boot Loader section. |
| 2 |
1 |
0 |
SPM is not allowed to write to the
Boot Loader section. |
| 3 |
0 |
0 |
SPM is not allowed to write to the
Boot Loader section, and LPM executing from the Application section is not
allowed to read from the Boot Loader section. If Interrupt Vectors are placed
in the Application section, interrupts are disabled while executing from the
Boot Loader section. |
| 4 |
0 |
1 |
LPM executing from the Application
section is not allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Application section, interrupts are disabled while
executing from the Boot Loader section. |
Note:
- Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
- '1' means unprogrammed; '0' means
programmed.