Sleep Modes

The following Table shows the different sleep modes and their wake-up sources.

Table 1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Sleep Mode	Active Clock Domains					Oscillators		Wake-up Sources
Sleep Mode	clk_CPU	clk_FLASH	clk_IO	clk_ADC	clk_ASY	Main Clock Source Enabled	Timer Oscillator  Enabled	INT and PCINT	TWI Address Match	Timer2	SPM/EEPROM  Ready	ADC	WDT	Other I/O
Idle			Yes	Yes	Yes	Yes	Yes⁽²⁾	Yes	Yes	Yes	Yes	Yes	Yes	Yes
ADC Noise  Reduction				Yes	Yes	Yes	Yes⁽²⁾	Yes⁽³⁾	Yes	Yes⁽²⁾	Yes	Yes	Yes
Power-down								Yes⁽³⁾	Yes				Yes
Power-save					Yes	Yes	Yes⁽²⁾	Yes⁽³⁾	Yes	Yes			Yes
Standby⁽¹⁾						Yes		Yes⁽³⁾	Yes				Yes
Extended Standby					Yes⁽²⁾	Yes	Yes⁽²⁾	Yes⁽³⁾	Yes	Yes			Yes

Note:

Only recommended with external crystal or resonator selected as clock source.
If Timer/Counter2 is running in asynchronous mode.
For INT1 and INT0, only level interrupt.

To enter any of the six sleep modes, the Sleep Enable bit in the Sleep Mode Control Register (SMCR.SE) must be written to '1' and a SLEEP instruction must be executed. Sleep Mode Select bits (SMCR.SM[2:0]) select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.

Note: The block diagram in the section System Clock and Clock Options provides an overview over the different clock systems in the device, and their distribution. This figure is helpful in selecting an appropriate sleep mode.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.