Timer/Counter 1 Interrupt Mask Register
Name:
TIMSK1
Offset:
0x6F
Reset:
0x00
Access:
-
Bit76543210
ICIEOCIEBOCIEATOIE
AccessR/WR/WR/WR/W
Reset0000

Bit 5 – ICIE: Input Capture Interrupt Enable

Input Capture Interrupt Enable

When this bit is written to '1', and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF Flag, located in TIFR1, is set.

Bit 2 – OCIEB: Output Compare B Match Interrupt Enable

Output Compare B Match Interrupt Enable

When this bit is written to '1', and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCFB Flag, located in TIFR1, is set.

Bit 1 – OCIEA: Output Compare A Match Interrupt Enable

Output Compare A Match Interrupt Enable

When this bit is written to '1', and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCFA Flag, located in TIFR1, is set.

Bit 0 – TOIE: Overflow Interrupt Enable

Overflow Interrupt Enable

When this bit is written to '1', and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 1 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV Flag, located in TIFR1, is set.