When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter
Synchronization mode. In this mode, the value that is written to the PSRASY and
PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals
asserted. This ensures that the corresponding Timer/Counters are halted and can be
configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are
cleared by hardware, and the Timer/Counters start counting
simultaneously.
Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset.
This bit is normally cleared immediately by hardware. If the bit is written when
Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the
prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is
set.
Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler
will be Reset. This bit is normally cleared immediately by hardware, except if the
TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler
and a reset of this prescaler will affect both timers.