- The Clock Failure Detector (CFD) allows the user to monitor the low-power crystal oscillator or external clock signal
- When the XOSC is working, the ‘CKSEL to clock sel’, as shown in the figure below, will be ‘CKSEL fuse’, which will be selected and the appropriate clock will be used as the system clock
- XOSC failure is monitored by the CFD circuit, which works in 128 kHz
- Once the failure is detected, the calibrated RC oscillator is enabled
- XFDIF interrupt will be raised. This interrupt is enabled by the XFDIE bit of the XFDCSR register.
- If the XOSC fails, the selected clock
will be 4
'b0010(hard-coded, as shown in the figure below), which is the value of the calibrated RC. The output of the calibrated RC will be used as the system clock. - The fallback clock will be 1 MHz. The figure shows system clock generation with CFD mechanism.
- The clock can be modified by changing the prescaler after clock switching
- CFD will be automatically disabled when the chip enters Power-Save/Down sleep mode and then enabled when the chip returns to Active mode
- A Reset must be provided to use the original clock source
- The user can change the clock frequency by configuring the prescaler after switching the clock
- CFD will be enabled only if the system frequency is above 256 kHz
- During start-up, CFD will be enabled by default. If the external clock is not provided, the device will automatically switch to the 1 MHz calibrated RC Oscillator output.
Figure 1. System Clock Generation with CFD
Mechanism
