Configuration

Figure 1. Master-Slave Relations High-Speed Bus Matrix
Table 1. High Speed Bus Matrix Masters
High-Speed Bus Matrix Masters Master ID
CM0+ - Cortex M0+ Processor 0
DSU - Device Service Unit 1
DMAC - Direct Memory Access Controller / Data Access 2
Table 2. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix Slaves Slave ID
Internal Flash Memory 0
SRAM Port 0 - CM0+ Access 1
SRAM Port 1 - DSU Access 2
AHB-APB Bridge B 3
AHB-APB Bridge A 4
AHB-APB Bridge C 5
SRAM Port 2 - DMAC Data Access 6
Parent topic: High-Speed Bus System