A unique feature of the integrated CVD hardware is the software adjustable additional capacitance that can be added in parallel with CHOLD. The user can add an additional 1-31 pF by writing to the ADCAP register. Refer to the device data sheet for the specific register values and the corresponding added capacitance. In the event where the ADCAP register is left empty, no additional capacitance will be added. The additional capacitance is only connected during the precharge and acquisition stages and does not affect ADC2 performance or timing. When used in CVD applications this feature allows the user to better match the internal sample capacitance to the external conductive sensor. Matching the internal and external capacitance can help improve sensitivity and performance of the sensor. Refer to ADC Module Setup for CVD Measurement, which shows how to add additional sample and hold capacitance.