CVD Acquisition Control

Once C_HOLD and the external capacitive sensor are precharged to opposite known voltages, the line between the two is connected, effectively forming a capacitive voltage divider. The reconnection of C_HOLD and the external sensor that forms the voltage divider signifies the beginning of the acquisition stage. During the acquisition stage, the previously opposite voltage levels between the two will equalize to a middle value based upon the relationship of C_HOLD and the external capacitance on the sensor. After the acquisition stage, the ADC² samples the voltage level of C_HOLD, which represents the relative capacitance measured on the analog channel.

The acquisition stage of the CVD operation is an optional period to allow C_HOLD to charge or discharge from the selected analog channel before the ADC² collects the sample. The ADC² module offers the flexibility to set the acquisition time during CVD operation to allow charge averaging between the precharged channel and the C_HOLD capacitor. The user can control the acquisition time (charge share time) by writing to the ADACQL/H register pair. For the ADC² to meet the specified accuracy, C_HOLD must be allowed to fully charge to the analog input channel voltage level. There are several things that can influence the minimum required time for acquisition. Refer to the device data sheet for more information about ADC acquisition requirements. Example 2-2 demonstrates how to configure the acquisition time for CVD operation using the PIC18F25K42 microcontroller. Example 2-3 provides an example of how the one would perform a CVD measurement using the ADC module. Note that minor changes may need to be made for this example to work on other PIC devices with this CVD feature.

ADC Module Setup for CVD Measurement

// ADCC & CVD Initialize

ADRPT = 0x1F;   // ADC Repeat Threshold Bits;
ADACQL = 0x0A;  // ADC Acquisition Time Control Register (Low);
ADACQH = 0x00;  // ADC Acquisition Time Control Register (High);
ADCAP = 0x00;   // Additional Sample and Hold Capacitance; 
ADPREL = 0x0A;  // ADC Pre-charge Time Control Register (Low);
ADPREH = 0x00;  // ADC Pre-charge Time Control Register (High);
ADCON1 = 0x00;  // ADC Control Register 1;
        // ADCON1bits.PPOL = Precharge Polarity Bit;
        // ADCON1bits.IPEN = ADC Inverted Precharge Polarity Enable Bit;
        // ADCON1bits.GPOL = Guard Ring Polarity Selection Bit;
        // ADCON1bits.DSEN = Double Sample Enable Bit;
ADCON2 = 0xD3;  // ADC Control Register 2;
ADCON3 = 0x00;  // ADC Control Register 3;
ADREF = 0x00;   // ADC Voltage Reference Selection Register;
ADCLK = 0x00;   // ADC Clock Selection Register;
ADCON0 = 0x84;  // ADC Control Register 0;
ADACT = 0x00;   // ADC Auto Conversion Trigger Control Register;